FPGA AI Suite: Compiler Reference Manual

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ID 768972
Date 9/06/2024
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Document Table of Contents
Document Table of Contents x
1. FPGA AI Suite Compiler Reference Manual 2. About the FPGA AI Suite Compiler 3. FPGA AI Suite Compiler Use Modes 4. FPGA AI Suite Compiler Command Line Options 5. Compiler Inputs and Outputs A. FPGA AI Suite Compiler Reference Manual Archives B. FPGA AI Suite Compiler Reference Manual Document Revision History
3. FPGA AI Suite Compiler Use Modes x
3.1. Compiling a Graph 3.2. Generating Artifacts for DDR-Free Operation 3.3. Estimating the Performance of a Graph 3.4. Estimating the Area of an Architecture 3.5. Generating an Optimized Architecture
3.5. Generating an Optimized Architecture x
3.5.1. Generating an Architecture for Highest Performance 3.5.2. Generating an Architecture Optimized for a Frame Rate Target Value
4. FPGA AI Suite Compiler Command Line Options x
4.1. Inputs (dla_compiler Command Options) 4.2. Outputs (dla_compiler Command Options) 4.3. Reporting (dla_compiler Command Options) 4.4. Compilation Options (dla_compiler Command Options) 4.5. Architecture Options (dla_compiler Command Options) 4.6. Architecture Optimizer Options (dla_compiler Command Options) 4.7. Analyzer Tool Options (dla_compiler Command Options) 4.8. Miscellaneous Options (dla_compiler Command Options)
5. Compiler Inputs and Outputs x
5.1. FPGA AI Suite Input File Formats 5.2. FPGA AI Suite Compiler Graph Export Formats 5.3. The Partitioning Table Report 5.4. Model Analyzer Reports
1. FPGA AI Suite Compiler Reference Manual
2. About the FPGA AI Suite Compiler
3. FPGA AI Suite Compiler Use Modes
4. FPGA AI Suite Compiler Command Line Options
5. Compiler Inputs and Outputs
A. FPGA AI Suite Compiler Reference Manual Archives
B. FPGA AI Suite Compiler Reference Manual Document Revision History

3.2. Generating Artifacts for DDR-Free Operation

When a graph is compiled with an architecture file that has the enable_parameter_rom FPGA AI Suite IP block configuration option enabled, the FPGA AI Suite compiler (dla_compiler) produces a set of memory initialization (.mif) files in the current working directory. These files are required to build the bitstream for DDR-free operation and to run software inference. You do not need to specify any additional compiler options when compiling an architecture with DDR-free operation enabled.

For an architecture with DDR-free operation enable, the compiler produces the following files:
  • ./memoryless_filter_hw*.mif

    Contain the graph filters that are used to build the bitstream for DDR-free operation.

  • ./memoryless_bias_scale_hw*.mif

    Contain the graph biases and scaling factors used to build the bitstream for DDR-free operation

  • ./memoryless_filter_ref*.mif

    Contain the graph filters in software-reference form.

  • ./memoryless_bias_scale_ref*.mif

    Contains the graph biases and scaling factors in software-reference format

  • ./memoryless_config.mif

    Stores the FPGA AI Suite instructions for the compiled graph.

The filter and bias/scale .mif files are postfixed with an integer that represents the PE that the parameters are loaded into.

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