Nios® V Embedded Processor Design Handbook

ID 726952
Date 5/26/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4. Nios® V Processor Configuration and Booting Solutions

You can configure the Nios® V processor to boot and execute software from different memory locations. The boot memory is the Quad Serial Peripheral Interface (QSPI) flash or On-Chip Memory (OCRAM).