Nios® V Embedded Processor Design Handbook

ID 726952
Date 5/26/2023
Public

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8.4. Operating the Example Design

To display the application messages, the example design utilizes the JTAG UART Intel FPGA IP. You can begin the display message by using the following command:

juart-terminal
Figure 96. Output Result from PE1
Figure 97. Output Result from PE2