Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit User Guide

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ID 721605
Date 5/31/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Power Up the Development Kit 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit User Guide A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Quartus® Prime Software and Driver Installation 2.2. Design Examples
3. Power Up the Development Kit x
3.1. Default Settings 3.2. Power Up 3.3. Performing Board Restore
3.3. Performing Board Restore x
3.3.1. Restore Board System MAX® 10 with Default Factory Image 3.3.2. Restoring Board QSPI Flash with Default Factory Image
4. Board Test System x
4.1. Set Up BTS GUI Running Environment 4.2. Test the Functionality of the Development Kit 4.3. Control On-Board Clock through Clock Controller GUI 4.4. Monitor On-Board Power Regulator through Power Monitor GUI 4.5. BTS Test Areas 4.6. Identify Test Pass or Fail-based on BTS GUI Test Status
4.1. Set Up BTS GUI Running Environment x
4.1.1. Download OpenJDK 4.1.2. Download OpenJFX 4.1.3. Install OpenJDK and OpenJFX 4.1.4. Install Quartus® Prime Software 4.1.5. Run BTS GUI
4.2. Test the Functionality of the Development Kit x
4.2.1. The Bottom Info Bar 4.2.2. The Configure Menu 4.2.3. The Sys Info Tab 4.2.4. The GPIO Tab 4.2.5. The XCVR Tab 4.2.6. The Memory Tab
4.2.5. The XCVR Tab x
4.2.5.1. The QSFPDD NRZ Tab 4.2.5.2. The QSFPDD PAM4 Tab 4.2.5.3. The FMCA NRZ Tab 4.2.5.4. The FMCB NRZ Tab 4.2.5.5. The QSFPDD800 PAM4 Tab 4.2.5.6. The MXPM NRZ Tab 4.2.5.7. The MXPM PAM4 Tab 4.2.5.8. The SDI Tab
5. Development Kit Hardware and Configuration x
5.1. Configure FPGA and Access HPS Debug Access Port by JTAG 5.2. Configure the FPGA Device Using the AS Mode (Default Mode) 5.3. Configure the FPGA Device Using the Avalon® -ST Mode 5.4. Daughter Cards
5.4. Daughter Cards x
5.4.1. HPS Out of Box Experience (OOBE) Daughter Card
6. Custom Projects for the Development Kit x
6.1. Add SmartVID Settings in the Quartus® Prime QSF File 6.2. Golden Top
A. Development Kit Components x
A.1. System Management A.2. Power A.3. Clocks A.4. General Input/Output A.5. Memory Interfaces A.6. Communication Interfaces A.7. Daughter Cards A.8. Connectors and Cables
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Power Up the Development Kit
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit User Guide
A. Development Kit Components
B. Additional Information

A.6. Communication Interfaces

MCIO Port

The MCIO slot is a PCIe* Gen4 x4 port which fans out from Agilex™ 7 FPGA I-Series F-Tile. This port is designed to meet the standard MCIO pinout. System MAX® 10 acts as the board management controller (BMC) of the development kit. It manages power-up reset for both PCIe* root port and PCIe* endpoint. PCIE_PERSTn_A signal can act as output and input respectively.

Table 13.  MCIO Port
Schematic Signal Name Description
PCIE_PERSTn_A PCIe* endpoint/root port reset
PCIE_ALERTn_A PCIe* Alert
PCIE_100M_REF_AP/AN PCIe* reference clock
PCIE_SCL_A/SDA_A PCIe* I2C bus
PCIE_TX_P/N[0:3] Transceiver TX
PCIE_RX_P/N[0:3] Transceiver RX

MCIO x4 Connector

The recommended MCIO cable to use with MCIO connector (Uxx) is NOT included as part of the development kit and must be acquired directly from third party supplier (Amphenol p/n = HMC74-0631).

QSFPDD

Agilex™ 7 I-Series Development Kit supports 2x QSFPDD ports. QSFDD port fans out from Agilex™ 7 FPGA I-Series F-Tile (FGT). All 8 channels per QSFPDD can run up to 32G NRZ and 58G PAM4.

Table 14.  QSFPDD Connector 0 (13C/J27)
Schematic Signal Name Description
QSFPDD0_3V3_MODPRS_L Module present
QSFPDD0_3V3_RESET_L Module reset
QSFPDD0_3V3_MODSEL_L Mode select
QSFPDD0_3V3_LPMODE Initial mode
QSFPDD0_3V3_INT_L Interrupt
I2C_QSFPDD0_3V3_SCL I2C clock
I2C_QSFPDD0_3V3_SDA I2C data
QSFPDD0_TX_P/N[0:7] Transceiver TX
QSFPDD0_RX_P/N[0:7] Transceiver RX
Table 15.  QSFPDD Connector 1 (13A/J48)
Schematic Signal Name Description
QSFPDD1_3V3_MODPRS_L Module present
QSFPDD1_3V3_RESET_L Module reset
QSFPDD1_3V3_MODSEL_L Mode select
QSFPDD1_3V3_LPMODE Initial mode
QSFPDD1_3V3_INT_L Interrupt
I2C_QSFPDD1_3V3_SCL I2C clock
I2C_QSFPDD1_3V3_SDA I2C data
QSFPDD1_TX_P/N[0:7] Transceiver TX
QSFPDD1_RX_P/N[0:7] Transceiver RX

QSFPDD800/MXP

Agilex™ 7 I-Series Development Kit supports 1x QSFPDD800 port. QSFDD800 port fans out from Agilex™ 7 FPGA I-Series F-Tile (FHT). The FHT tile from bank 13A and 13C can run up to 116G PAM4. 4 FHT lanes from bank 13C is terminated directly to QSFPDD800 connector lanes [0:3] (J22).

Table 16.  QSFPDD800 (13A)
Schematic Signal Name Description
QSFPDD800_3V3_MODPRS_L Module present
QSFPDD800_3V3_RESET_L Module reset
QSFPDD800_3V3_MODSEL_L Mode select
QSFPDD800_3V3_LPMODE Initial mode
QSFPDD800_3V3_INT_L Interrupt
I2C_QSFPDD800_3V3_SCL I2C clock
I2C_QSFPDD800_3V3_SDA I2C data
QSFPDD800_TX_P/N[0:3] Transceiver TX
QSFPDD800_RX_P/N[0:3] Transceiver RX

Four FHT lanes from bank 13A are terminated to MXPM connector (J2).Other lanes [4:7] of QSFPDD800 connector is terminated to MXPM connector (J8). For x8 QSFPDD800 topology, 1-1 cable between J2 and J8 need to be used.

Figure 36. MXPM Cable

MXP

MXP port fan out from Agilex™ 7 FPGA I-Series F-Tile (13A). All four channels can run up to 32G NRZ and 58G PAM4.

Table 17.  MXP
Schematic Signal Name Description
FGT_MXPM_TX_P/N_[0:3] Transceiver TX
FGT_MXPM_RX_P/N_[0:3] Transceiver RX

FMC+ Connector

Agilex™ 7 I-Series Development Kit supports 2x FMC+ slots for functional expandability. The x16 FGT lanes from bank 12C and 12A are terminated to FMC-A (J7) and FMC-B (J9) connectors, respectively. Auxiliary signals are controlled by the system MAX® 10.

SDI Connector

1x FGT channel (13C/Q0/CH3) been terminated to the HD-BNC TX (J1) and RX (J32) connectors to support up to 12G SDI. System MAX® 10 acts as an I2C master for both SDI driver and receiver, along with control signals.

USB Type-C Connector

Agilex™ 7 I-Series Development Kit has hardware support for the USB Type-C connector, which supports DP1.4 specification or USB 3.1 functionality through MUX (TUSB1146). This feature is yet to be validated and implemented.

Serial Buses

SDM I/Os (SDM_IO0/12) and MAX® 10 I/Os (VCCL_SDA/SCL) share the same I2C bus which communicate with Agilex™ 7 FPGA core regulators. By default, SDM acts as SmartVID master and system MAX® 10 act as Power GUI master in this chain.

System MAX® 10 I/Os (PMB_SDA/SCL) manages the second I2C bus which access all I2C slave regulator except Agilex™ 7 FPGA core regulators.

System MAX® 10 supports I2C master dedicated to clock-related devices (CLK_I2C_SDA/SCL), which manages 3# clock devices and also connected to the HPS I/Os (HPS_GPIO30/31) through level translator.

Another I2C master instance from system MAX® 10 (VCXO_I2C_SDA/SCL) controls the on board VCXO and Si5394 clock generator.

Agilex™ 7 FPGA also manages QSFPDD800, 2x QSFPDD, 2DPC DIMM I2C buses, SDI transceivers, and ZL30733 clock synthesizer device.

Table 18.   I2C Debug Headers
Schematic Signal Name Description
PMB_SCL/SDA VRs I2C header J41
CLK_I2C_SDA/SCL_3V3 System MAX® 10 clock I2C bus header J42
ZL_I2C_SDA/SCL ZL30733 I2C access header J21
Figure 37.  I2C Serial Bus ( Intel® Enpirion® ) DK-SI-AGI027FB and DK-SI-AGI027FES
Figure 38.  I2C Serial Bus (Not Intel® Enpirion® ) DK-SI-AGI027FA and DK-SI-AGI027FC
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