Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit User Guide

ID 721605
Date 5/31/2024
Public
Document Table of Contents

A.4. General Input/Output

Table 10.   MAX® 10 and FPGA
Schematic Signal Name Description
F_GPIO0 The value of filtered user_pb[0]
F_GPIO1 The value of filtered user_pb[1]
F_GPIO2 MCIO_PERST in RP mode
F_GPIO3 FMC_A_PERST in RP mode
F_GPIO4 FMC_B_PERST in RP mode
F_GPIO5 Status of SYS_SW3 from MAX® 10
F_GPIO6 Reserved
F_GPIO7 Reserved
F_GPIO8 Reserved
F_GPIO9 Reserved
F_GPIO10 Reserved
F_GPIO11 Reserved
F_GPIO12 Reserved
Table 11.  System MAX® 10
Schematic Signal Name Description
SYS_LED0/D9 PGM_LED0 for Avalon® -ST configuration
SYS_LED1/D11 PGM_LED1 for Avalon® -ST configuration
SYS_LED2/D13 PGM_LED2 for Avalon® -ST configuration
SYS_LED3/D15 MAX_ERROR for Avalon® -ST configuration
SYS_LED4/D10 MAX_LOAD for Avalon® -ST configuration
SYS_LED5/D12 MAX_CONF_DONE for Avalon® -ST configuration
SYS_LED6/D14 Reserved
SYS_LED7/D16 Reserved
SYS_PB0/S11 MAX_RESETn
SYS_PB1/S12 FPGA_RESETn
SYS_PB2/S13 HPS_COLD_RESETn
SYS_PB3/S14 Power recycle
SYS_PB4/S16 PGM_SEL for Avalon® -ST configuration
SYS_PB5/S17 PGM_CFG for Avalon® -ST configuration
clk_i2c_en0

Before power ok: 0

After power ok: S_control_gui[2], =1 by default

clk_i2c_en1 Stuck at GND
VCCL_I2C_EN

Before power ok: 0

After power ok: S_control_gui[1], =1 by default

dimm_io_en

Before power ok: 0

After power ok: 1

zl_i2c_en

Before power ok: 0

After power ok: S_control_gui[3], =0 by default

si5394_rstn

When input globe resetn active: 0

When input globe resetn release: S_control_gui[13], =1 by default

si5394_oe_n

Before power ok: 1

After power ok: S_control_gui[14], =0 by default

si5391_rstn

When input globe resetn active: 0

When input globe resetn release: S_control_gui[9], =1 by default

si5394_lol Store in status_gui bit3
si5394_int_n Store in status_gui bit2
si5391_oen

Before power ok: 1

After power ok: S_control_gui[10], =0 by default

si5391_b_rstn

When input globe resetn active: 0

When input globe resetn release: S_control_gui[11], =1 by default

si5391_b_oen

Before power ok: 1

After power ok: S_control_gui[12], =0 by default

usb2_resetn

Before power ok: 0

After power ok: S_control_gui[15], =1 by default

usb_mux_reset

Before power ok: 1

After power ok: S_control_gui[16], =0 by default

mux_sel0

system_info_slv_data_write_0[0]=1 : controlled by system_info_slv_data_write_1[0]

system_info_slv_data_write_0[0]=0 : controlled by MUX_DIP_SW10

mux_sel1

system_info_slv_data_write_0[1]=1 : controlled by system_info_slv_data_write_1[1]

system_info_slv_data_write_0[1]=0 : controlled by SYS_SW1

mux_sel2

system_info_slv_data_write_0[2]=1 : controlled by system_info_slv_data_write_1[2]

system_info_slv_data_write_0[2]=0 : controlled by MUX_DIP_SW0

mux_sel3

system_info_slv_data_write_0[3]=1 : controlled by system_info_slv_data_write_1[3]

system_info_slv_data_write_0[3]=0 : controlled by MUX_DIP_SW1

mux_sel4

system_info_slv_data_write_0[4]=1 : controlled by system_info_slv_data_write_1[4]

system_info_slv_data_write_0[4]=0 : controlled by MUX_DIP_SW2

mux_sel5

system_info_slv_data_write_0[5]=1 : controlled by system_info_slv_data_write_1[5]

system_info_slv_data_write_0[5]=0 : controlled by MUX_DIP_SW3

mux_sel6

system_info_slv_data_write_0[6]=1 : controlled by system_info_slv_data_write_1[6]

system_info_slv_data_write_0[6]=0 : controlled by MUX_DIP_SW9

mux_sel7

system_info_slv_data_write_0[7]=1 : controlled by system_info_slv_data_write_1[7]

system_info_slv_data_write_0[7]=0 : controlled by SYS_SW2

mux_sel8

system_info_slv_data_write_0[8]=1 : controlled by system_info_slv_data_write_1[8]

system_info_slv_data_write_0[8]=0 : controlled by MUX_DIP_SW11

mux_sel9

system_info_slv_data_write_0[9]=1 : controlled by system_info_slv_data_write_1[9]

system_info_slv_data_write_0[9]=0 : controlled by SYS_SW3

mux_sel10

system_info_slv_data_write_0[10]=1 : controlled by system_info_slv_data_write_1[10]

system_info_slv_data_write_0[10]=0 : controlled by MUX_DIP_SW4

mux_sel11

system_info_slv_data_write_0[11]=1 : controlled by system_info_slv_data_write_1[11]

system_info_slv_data_write_0[11]=0 : controlled by MUX_DIP_SW5

mux_sel12

system_info_slv_data_write_0[12]=1 : controlled by system_info_slv_data_write_1[12]

system_info_slv_data_write_0[12]=0 : controlled by MUX_DIP_SW6

mux_sel13

system_info_slv_data_write_0[13]=1 : controlled by system_info_slv_data_write_1[13]

system_info_slv_data_write_0[13]=0 : controlled by MUX_DIP_SW8

mux_sel14

system_info_slv_data_write_0[14]=1 : controlled by system_info_slv_data_write_1[14]

system_info_slv_data_write_0[14]=0 : controlled by MUX_DIP_SW7

mux_sel_zl

system_info_slv_data_write_0[15]=1 : controlled by system_info_slv_data_write_1[15]

system_info_slv_data_write_0[15]=0 : controlled by SYS_SW4

mcio_clk_enn

Before power ok: 1

After power ok: S_control_gui[7], =0 by default

mcio_clk_sel_epn

system_info_slv_data_write_0[16]=1 : controlled by S_control_gui[8], =0 by default

system_info_slv_data_write_0[16]=0 :

  • =0 when AGIB027R31B is Endpoint
  • =1 when AGIB027R31B is Root port
si5332_1_in[1:0] S_control_gui[5:4], =00 by default
si5332_1_in[2] 1'bZ
PTP_CLK_RST_n

Before power ok: 0

After power ok: S_control_gui[6], =1 by default

PTP_CLK_LOL Store in status_gui bit1
gpio0_ac0_zl_intn Store in status_gui bit0
Table 12.  UB2/PWR MAX® 10
Schematic Signal Name Description
FPGA_POK_LED FPGA Power Good
SYS_PWR_RSV0 Reserved GPIO between System MAX® 10 and Power MAX® 10. Used as I2C clock.
SYS_PWR_RSV1 Reserved GPIO between System MAX® 10 and Power MAX® 10. Used as I2C data.
SYS_PWR_RSV2 Reserved GPIO between System MAX® 10 and Power MAX® 10. It is the status of SYS_PB3.
SYS_PWR_RSV3 Reserved GPIO between System MAX® 10 and Power MAX® 10