Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit User Guide

ID 721605
Date 5/31/2024
Public
Document Table of Contents

A.1. System Management

Two MAX® 10 FPGAs (10M16SCU324C8G) are used for system management. System MAX® 10 acts as a system controller. It handles the FPGA Avalon® -ST configuration, I2C bus access, fan speed control, and system reset functions. The UB2/PWR MAX® 10 acts as the Power Manager and on-board JTAG controller. Refer to the following description for each function:

  • Power management: Control systems and FPGA power-up and optional power-down sequence (PDS), supervise power regulators/switches status and manage power faults, supervise temperature analog-to-digital converter (ADC) interrupt signals and manage temperature faults.
  • JTAG controller: Manage the JTAG chain topology, JTAG master source and JTAG slaves using S19/S20.
Table 7.  JTAG Master Sources
Schematic Signal Name Description
EXT_JTAG_TCK/TDO/TMS/TDI JTAG header J11 for Intel® FPGA Download Cable
FX2_Dp/n Input port J10 for on-board Intel® download circuit
HPS_GPIO[32:35] Mictor 38-pin header on the OOBE daughter card

Agilex™ 7 HPS JTAG can be accessed from either SDM dedicated JTAG pins or HPS dedicated I/Os. When it is accessed from SDM JTAG pins (FPGA_JTAG_TCK/TDO/TMS/TDI), SDM is chained with HPS inside FPGA. When it is accessed from HPS dedicated I/Os (HPS_GPIO[32:35]), HPS is chained externally by PCB traces.

Table 8.  JTAG Chain Topology Settings
Mode S20 [4:2] S19 [4] [3] [2] [1]

ON: Bypass from chain

OFF: Enable in chain

Function
000

ON/ON/ON (Default)

S19.1 (SDM+HPS)

S19.2 (System MAX® 10)

S19.3 (FMC_B)

S19.4 (FMC_A)

Mode 1: On-board Intel® download circuit act as the only JTAG Master. Chained HPS with SDM nodes internally.

Mode 3: External Intel® FPGA Download Cable act as the only JTAG Master. Chained HPS with SDM nodes internally.

001 ON/ON/OFF

SDM is always enabled in the JTAG chain.

S19.1 (HPS)

S19.2 (System MAX® 10)

S19.3 (FMC_B)

S19.4 (FMC_A)

Mode 2: On-board Intel® download circuit act as the only JTAG Master. Chained HPS with SDM nodes externally.

Mode 4: External Intel® FPGA Download Cable act as the only JTAG Master. Chained HPS with SDM node externally.

100 OFF/ON/ON

S19.1 (SDM)

S19.2 (System MAX® 10)

S19.3 (FMC_B)

S19.4 (FMC_A)

Mode 7: Both on-board Intel® download circuit and OOBE act as JTAG Masters.

Separated HPS and SDM JTAG chains, OOBE only drive HPS.

Mode 8: Both external Intel® FPGA Download Cable and OOBE JTAG act as JTAG Masters.

Separated HPS and SDM JTAG chains, OOBE only drive HPS.

Others N/A N/A Reserved