Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit User Guide

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ID 721605
Date 5/31/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Power Up the Development Kit 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit User Guide A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Quartus® Prime Software and Driver Installation 2.2. Design Examples
3. Power Up the Development Kit x
3.1. Default Settings 3.2. Power Up 3.3. Performing Board Restore
3.3. Performing Board Restore x
3.3.1. Restore Board System MAX® 10 with Default Factory Image 3.3.2. Restoring Board QSPI Flash with Default Factory Image
4. Board Test System x
4.1. Set Up BTS GUI Running Environment 4.2. Test the Functionality of the Development Kit 4.3. Control On-Board Clock through Clock Controller GUI 4.4. Monitor On-Board Power Regulator through Power Monitor GUI 4.5. BTS Test Areas 4.6. Identify Test Pass or Fail-based on BTS GUI Test Status
4.1. Set Up BTS GUI Running Environment x
4.1.1. Download OpenJDK 4.1.2. Download OpenJFX 4.1.3. Install OpenJDK and OpenJFX 4.1.4. Install Quartus® Prime Software 4.1.5. Run BTS GUI
4.2. Test the Functionality of the Development Kit x
4.2.1. The Bottom Info Bar 4.2.2. The Configure Menu 4.2.3. The Sys Info Tab 4.2.4. The GPIO Tab 4.2.5. The XCVR Tab 4.2.6. The Memory Tab
4.2.5. The XCVR Tab x
4.2.5.1. The QSFPDD NRZ Tab 4.2.5.2. The QSFPDD PAM4 Tab 4.2.5.3. The FMCA NRZ Tab 4.2.5.4. The FMCB NRZ Tab 4.2.5.5. The QSFPDD800 PAM4 Tab 4.2.5.6. The MXPM NRZ Tab 4.2.5.7. The MXPM PAM4 Tab 4.2.5.8. The SDI Tab
5. Development Kit Hardware and Configuration x
5.1. Configure FPGA and Access HPS Debug Access Port by JTAG 5.2. Configure the FPGA Device Using the AS Mode (Default Mode) 5.3. Configure the FPGA Device Using the Avalon® -ST Mode 5.4. Daughter Cards
5.4. Daughter Cards x
5.4.1. HPS Out of Box Experience (OOBE) Daughter Card
6. Custom Projects for the Development Kit x
6.1. Add SmartVID Settings in the Quartus® Prime QSF File 6.2. Golden Top
A. Development Kit Components x
A.1. System Management A.2. Power A.3. Clocks A.4. General Input/Output A.5. Memory Interfaces A.6. Communication Interfaces A.7. Daughter Cards A.8. Connectors and Cables
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Power Up the Development Kit
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit User Guide
A. Development Kit Components
B. Additional Information

A.1. System Management

Two MAX® 10 FPGAs (10M16SCU324C8G) are used for system management. System MAX® 10 acts as a system controller. It handles the FPGA Avalon® -ST configuration, I2C bus access, fan speed control, and system reset functions. The UB2/PWR MAX® 10 acts as the Power Manager and on-board JTAG controller. Refer to the following description for each function:

  • Power management: Control systems and FPGA power-up and optional power-down sequence (PDS), supervise power regulators/switches status and manage power faults, supervise temperature analog-to-digital converter (ADC) interrupt signals and manage temperature faults.
  • JTAG controller: Manage the JTAG chain topology, JTAG master source and JTAG slaves using S19/S20.
Table 7.  JTAG Master Sources
Schematic Signal Name Description
EXT_JTAG_TCK/TDO/TMS/TDI JTAG header J11 for Intel® FPGA Download Cable
FX2_Dp/n Input port J10 for on-board Intel® download circuit
HPS_GPIO[32:35] Mictor 38-pin header on the OOBE daughter card

Agilex™ 7 HPS JTAG can be accessed from either SDM dedicated JTAG pins or HPS dedicated I/Os. When it is accessed from SDM JTAG pins (FPGA_JTAG_TCK/TDO/TMS/TDI), SDM is chained with HPS inside FPGA. When it is accessed from HPS dedicated I/Os (HPS_GPIO[32:35]), HPS is chained externally by PCB traces.

Table 8.  JTAG Chain Topology Settings
Mode S20 [4:2] S19 [4] [3] [2] [1]

ON: Bypass from chain

OFF: Enable in chain

 Function
000

ON/ON/ON (Default)

S19.1 (SDM+HPS)

S19.2 (System MAX® 10)

S19.3 (FMC_B)

S19.4 (FMC_A)

Mode 1: On-board Intel® download circuit act as the only JTAG Master. Chained HPS with SDM nodes internally.

Mode 3: External Intel® FPGA Download Cable act as the only JTAG Master. Chained HPS with SDM nodes internally.

001 ON/ON/OFF

SDM is always enabled in the JTAG chain.

S19.1 (HPS)

S19.2 (System MAX® 10)

S19.3 (FMC_B)

S19.4 (FMC_A)

Mode 2: On-board Intel® download circuit act as the only JTAG Master. Chained HPS with SDM nodes externally.

Mode 4: External Intel® FPGA Download Cable act as the only JTAG Master. Chained HPS with SDM node externally.

100 OFF/ON/ON

S19.1 (SDM)

S19.2 (System MAX® 10)

S19.3 (FMC_B)

S19.4 (FMC_A)

Mode 7: Both on-board Intel® download circuit and OOBE act as JTAG Masters.

Separated HPS and SDM JTAG chains, OOBE only drive HPS.

Mode 8: Both external Intel® FPGA Download Cable and OOBE JTAG act as JTAG Masters.

Separated HPS and SDM JTAG chains, OOBE only drive HPS.

Others N/A N/A Reserved
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