Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit User Guide

ID 721605
Date 5/31/2024
Public
Document Table of Contents

3.1. Default Settings

The Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit ships with its board switches preconfigured to support the design examples in the kit. If you suspect your board might not be correctly configured with the default settings, follow the instructions in the factory default switch settings table to return to its factory settings before proceeding ahead.

Note: X refers to Don't Care in the table below.
Note: Don't set the switches when the power is on. Only set the switches after the power is off.
Table 4.  Factory Default Switch Settings
Switch Default Position Default Function
S19 [1:4] OFF/OFF/ON/ON System MAX® 10 and FPGA selected in JTAG chain.
S20 [1:4] ON/ON/ON/ON

Mode 1: On-board Intel® download circuit act as the only JTAG master.

Chained HPS with SDM nodes internally.

S9 [1:4] ON/OFF/OFF/X

Configuration mode setting bits:

AS - Fast mode

S10 [1:4] ON/ON/ON/ON

SYS_SW[0:3]

  • SYS_SW[0]—Factory Loadn
  • ‘0’—Load image from Page 0 of the QSPI
  • SYS_SW[1]—MUX_SEL1
  • SYS_SW[2]—MUX_SEL7
  • SYS_SW[3]—MUX_SEL9
S15 [1:4] ON/ON/ON/OFF

SYS_SW[4:7]

  • SYS_SW[4]—MUX_SEL_ZL
  • SYS_SW[5]—FMC-A PCIe RP/EP Select
    • “0”: RP (Default)
    • “1”: EP
  • SYS_SW[6]—FMC-B PCIe RP/EP Select
    • “0”: RP (Default)
    • “1”: EP
  • SYS_SW[7]—MCIO PCIe RP/EP Select
    • “0”: RP
    • “1”: EP (Default)
S1 [1:4] OFF/OFF/OFF/OFF User Switch [0:3]
S6 [1:4] OFF/OFF/OFF/OFF User Switch [4:7]
S22 [1:4] ON/ON/ON/ON

MUX_DIP_SW[0:3]

  • MUX_DIP_SW0—MUX_SEL2
  • MUX_DIP_SW1—MUX_SEL3
  • MUX_DIP_SW2—MUX_SEL4
  • MUX_DIP_SW3—MUX_SEL5

Set to "ON" by default to select on-board clock as input.

S23 [1:4] ON/ ON / ON / ON

MUX_DIP_SW[4:7]

  • MUX_DIP_SW4—MUX_SEL10
  • MUX_DIP_SW5—MUX_SEL11
  • MUX_DIP_SW6—MUX_SEL12
  • MUX_DIP_SW7—MUX_SEL14

Set “0”/closed by default for on-board clock as input.

S4 [1:4] ON/ ON / ON / ON

MUX_DIP_SW[8:11]

  • MUX_DIP_SW8—MUX_SEL13
  • MUX_DIP_SW9—MUX_SEL6
  • MUX_DIP_SW10—MUX_SEL0
  • MUX_DIP_SW11—MUX_SEL8

Set “0”/closed by default for on-board clock as input.