Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit User Guide

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ID 721605
Date 5/31/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Power Up the Development Kit 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit User Guide A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Quartus® Prime Software and Driver Installation 2.2. Design Examples
3. Power Up the Development Kit x
3.1. Default Settings 3.2. Power Up 3.3. Performing Board Restore
3.3. Performing Board Restore x
3.3.1. Restore Board System MAX® 10 with Default Factory Image 3.3.2. Restoring Board QSPI Flash with Default Factory Image
4. Board Test System x
4.1. Set Up BTS GUI Running Environment 4.2. Test the Functionality of the Development Kit 4.3. Control On-Board Clock through Clock Controller GUI 4.4. Monitor On-Board Power Regulator through Power Monitor GUI 4.5. BTS Test Areas 4.6. Identify Test Pass or Fail-based on BTS GUI Test Status
4.1. Set Up BTS GUI Running Environment x
4.1.1. Download OpenJDK 4.1.2. Download OpenJFX 4.1.3. Install OpenJDK and OpenJFX 4.1.4. Install Quartus® Prime Software 4.1.5. Run BTS GUI
4.2. Test the Functionality of the Development Kit x
4.2.1. The Bottom Info Bar 4.2.2. The Configure Menu 4.2.3. The Sys Info Tab 4.2.4. The GPIO Tab 4.2.5. The XCVR Tab 4.2.6. The Memory Tab Start Stop Reset Performance Indicators Test Control Error Control
4.2.5. The XCVR Tab x
4.2.5.1. The QSFPDD NRZ Tab 4.2.5.2. The QSFPDD PAM4 Tab 4.2.5.3. The FMCA NRZ Tab 4.2.5.4. The FMCB NRZ Tab 4.2.5.5. The QSFPDD800 PAM4 Tab 4.2.5.6. The MXPM NRZ Tab 4.2.5.7. The MXPM PAM4 Tab 4.2.5.8. The SDI Tab
5. Development Kit Hardware and Configuration x
5.1. Configure FPGA and Access HPS Debug Access Port by JTAG 5.2. Configure the FPGA Device Using the AS Mode (Default Mode) 5.3. Configure the FPGA Device Using the Avalon® -ST Mode 5.4. Daughter Cards
5.4. Daughter Cards x
5.4.1. HPS Out of Box Experience (OOBE) Daughter Card
6. Custom Projects for the Development Kit x
6.1. Add SmartVID Settings in the Quartus® Prime QSF File 6.2. Golden Top
A. Development Kit Components x
A.1. System Management A.2. Power A.3. Clocks A.4. General Input/Output A.5. Memory Interfaces A.6. Communication Interfaces A.7. Daughter Cards A.8. Connectors and Cables
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Power Up the Development Kit
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit User Guide
A. Development Kit Components
B. Additional Information

4.2.6. The Memory Tab

This tab allows you to read and write DDR4 DIMM-2A (DIMM-I) and DDR4 DIMM-2B (DIMM-II) memory on your board. RDIMMS only tests DIMM-II while RDIMMD tests DIMM-I and DIMM-II. Download the design through BTS Configure.

Figure 24. The RDIMMS Tab

The following sections describe controls on this tab.

Start

Initiates DDR4 memory transaction performance analysis.

Stop

Terminates transaction performance analysis.

Reset

Resets transaction performance analysis.

Performance Indicators

These controls display current transaction performance analysis information collected since you last clicked Start:

  • Write and Read performance bars: Show the percentage of maximum theoretical data rate that the requested transactions are able to achieve.
  • Write (MBps) and Read (MBps): Show the number of bytes analyzed per second.
  • Data Bus: 72 bits (8 bits ECC) wide, reference clock is 166.666 MHz, and the frequency is 1333.33 MHz double data rate 2666.66 MT/s.

Test Control

  • Test Size: You can choose the size of the memory to test. The available options are 64 KB, 256 KB, 1 MB, 16 MB, 64 MB, 256 MB, 1 GB, 4 GB, 8 GB, and 16GB (default).
  • Offset (Hex): You can define the memory start address to test.
  • Test Mode: Infinite Read and Write (default), Single Read and Write.
  • Test Pattern: PRBS (default), User Defined Constant, Walking ‘0’, Walking ‘1'.

Error Control

This control displays data errors detected during analysis and allows you to insert errors:

  • Detected Errors: Displays the number of data errors detected in the hardware.
  • Inserted Errors: Displays the number of errors inserted into the transaction stream.
  • Insert: Insert a one-word error into the transaction stream each time you click the button. Insert error is only enabled during transaction performance analysis.
  • Clear: Resets the Detected Errors counter and Inserted Errors counter to zeros.
Figure 25. The RDIMMD TabSimilar with RDIMMS. Test Size can be set to 32 GB with two RDIMMs.
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