Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit User Guide

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ID 721605
Date 2/28/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Intel® SoC EDS 2.3.3. Installing the Development Kit 2.3.4. Installing the Intel® FPGA Download Cable Driver
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Kit 3.3. Performing Board Restore
3.3. Performing Board Restore x
3.3.1. Restoring Board System MAX® 10 with Default Factory Image 3.3.2. Restoring Board QSPI Flash with Default Factory Image
4. Board Test System x
4.1. Set Up BTS GUI Running Environment 4.2. Test the Functionality of the Development Kit 4.3. Control On-Board Clock through Clock Controller GUI 4.4. Monitor On-Board Power Regulator through Power Monitor GUI 4.5. BTS Test Areas 4.6. Identify Test Pass or Fail based on BTS GUI Test Status
4.1. Set Up BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Setting Up the Quartus® Prime Software for BTS Operation 4.1.5. Running BTS GUI
4.2. Test the Functionality of the Development Kit x
4.2.1. The Bottom Info Bar 4.2.2. The Configure Menu 4.2.3. The Sys Info Tab 4.2.4. The GPIO Tab 4.2.5. The XCVR Tab 4.2.6. The Memory Tab
4.2.5. The XCVR Tab x
4.2.5.1. The QSFPDD NRZ Tab 4.2.5.2. The QSFPDD PAM4 Tab 4.2.5.3. The FMCA NRZ Tab 4.2.5.4. The FMCB NRZ Tab 4.2.5.5. The QSFPDD800 PAM4 Tab 4.2.5.6. The MXPM NRZ Tab 4.2.5.7. The MXPM PAM4 Tab 4.2.5.8. The SDI Tab
5. Development Kit Hardware and Configuration x
5.1. Configure FPGA and Access HPS Debug Access Port by JTAG 5.2. Configure the FPGA Device Using the AS Mode (Default Mode) 5.3. Configure the FPGA Device Using the Avalon® -ST Mode 5.4. Daughter Cards
5.4. Daughter Cards x
5.4.1. HPS Out of Box Experience (OOBE) Daughter Card
6. Custom Projects for the Development Kit x
6.1. Add SmartVID Settings in the Quartus® Prime QSF File 6.2. Golden Top
A. Development Kit Components x
A.1. System Management A.2. Power A.3. Clocks A.4. General Input/Output A.5. Memory Interfaces A.6. Communication Interfaces A.7. Daughter Cards A.8. Connectors and Cables
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

7. Document Revision History for the Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit User Guide

Document Version Changes
2024.05.31
  • Updated the description of Development Kit Version in Table: Ordering Inforamtion.
2023.04.10
  • Updated Ordering Information in Overview section.
  • Added Figure: Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit Board Image - DK-SI-AGI027FB and DK-SI-AGI027FES ( Intel® Enpirion® ) and Figure: Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit Board Image - DK-SI-AGI027FA and DK-SI-AGI027FC (Not Intel® Enpirion® ) in Overview section.
  • Updated list in Box Contents section.
  • Updated the FPGA maximum power supported by active heatsink/fan in Recommended Operating Conditions.
  • Updated Restore Board QSPI Flash with the Default Factory Image section.
  • Added Control On-board Clock through Clock Controller GUI section.
  • Added Control On-board Power Regulator through Power Monitor GUI section.
  • Added Post-tap 2 setting in The QSFPDD800 PAM4 Tab section.
  • Added The SDI Tab section.
  • Added description for Reset button in The Memory Tab section.
  • Updated description for Custom Projects for the Development Kit.
  • Updated Figure: BTS GUI.
  • Updated Figure: The Sys Info Tab.
  • Updated Figure: The Configure Menu.
  • Updated Figure: The Sys Info Tab.
  • Updated Figure: The GPIO Tab.
  • Updated Figure: The QSFPDD NRZ Tab.
  • Updated Figure: QSFPDD NRZ – PLL and Pattern Status.
  • Updated Figure: QSFPDD NRZ - PMA Setting.
  • Updated Figure: QSFPDD NRZ - Data Rate.
  • Updated Figure: The QSFPDD PAM4 Tab.
  • Updated Figure: The FMCA NRZ Tab.
  • Updated Figure: The FMCB NRZ Tab.
  • Updated Figure: The QSFPDD800 PAM4 Tab.
  • Updated Figure: The MXPM NRZ Tab.
  • Updated Figure: The MXPM PAM4 Tab.
  • Updated Figure: The RDIMMS Tab.
  • Updated Figure: The RDIMMD Tab.
  • Updated Figure: ZL30733.
  • Updated Figure: Power Monitor GUI.
  • Added constraint scripts for DK-SI-AGI027FA and DK-SI-AGI027FC, DK-SI-AGI027FB and DK-SI-AGI027FES in Add SmartVID Settings in the Intel Quartus Prime QSF File section.
  • Added Figure: Power Tree (Not Intel® Enpirion® ) DK-SI-AGI027FA and DK-SI-AGI027FC.
  • Added Figure: I2C Serial Bus (Not Intel Enpirion) DK-SI-AGI027FA and DK-SI-AGI027FC.
  • Updated product family name to " Intel Agilex® 7".
2023.03.02 Updated the MXMP breakout cable and MCIO cable part number details in Table: Connectors and Cables.
2022.09.30
  • Added UKCA in the Safety and Regulatory Information and Compliance Information sections.
  • Added the Lithium Ion Battery Warnings section.
  • Updated Table: Ordering Information.
  • Updated the Perform Board Restore section.
  • Updated step 3 in the Restore Board QSPI Flash with Default Factory Image section.
  • Updated the Control On-Board Clock through Clock Controller GUI section.
  • Updated step 1 and step 3 in the Configure FPGA and Access HPS Debug Access Port by JTAG section.
  • Updated the System Management section.
  • Updated the Power Cord Requirements section.
  • Updated the Safety Cautions section.
2022.04.07 Initial release.
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