F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide

ID 720987
Date 11/29/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.8. TOD Interface Signals

Table 17.  TOD Interface Signal
Signal Direction Width Description
master_pulse_per_second Out 1 Pulse per second (PPS) from the master PPS module. The signal stay asserted for 10 ms.
start_tod_sync[] In [NUM_CHANNELS] Use this signal to trigger the TOD synchronization process. The time-of-day of the local TOD is synchronized to the time-of-day of the master TOD. The synchronization process continues as long as this signal remains asserted.
pulse_per_second Out [NUM_CHANNELS] PPS from channel n. The signal stay asserted for 10 ms.