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1. About the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide
2. Quick Start Guide
3. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
4. Interface Signals Description
5. Configuration Registers Description
6. F-Tile Low Latency Ethernet 10G MAC Intel FPGA IP Design Example User Guide Archives
7. Document Revision History for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide
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2.4.1. Procedure
You can compile and test the design in the supported Intel FPGA development kit.
- Launch the Intel® Quartus® Prime Pro Edition software and open the design example project file. Select Processing > Start Compilation to compile the design example.
The timing constraints for the design example and the design components are automatically loaded during compilation.
- Connect the development board to the host computer.
Note: For the frequencies to set, refer to the Hardware Testing section in the respective design example chapter.
- In the Intel® Quartus® Prime Pro Edition software, select Tools > Programmer to configure the FPGA on the development board using the generated .sof file.
- In the Intel® Quartus® Prime software, select Tools > System Debugging Tools > System Console to launch the system console.
- Change the working directory to <Example Design>\hwtesting\system_console_fm.
- Initialize the design command list by running this command: source main.tcl.
You can now run any of the predefined hardware tests from the System Console.
Observe the test results displayed.