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1. About the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide
2. Quick Start Guide
3. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
4. Interface Signals Description
5. Configuration Registers Description
6. F-Tile Low Latency Ethernet 10G MAC Intel FPGA IP Design Example User Guide Archives
7. Document Revision History for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide
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2.1. Directory Structure
Figure 2. Directory Structure for the Design Example
Note: Only Synopsys VCS is supported in the current release.
Directory/File | Description |
---|---|
altera_eth_top.qpf | Intel® Quartus® Prime Pro Edition project file. |
altera_eth_top.qsf | Intel® Quartus® Prime Pro Edition settings file. |
altera_eth_top.sv | Design example top-level HDL. |
altera_eth_top.sdc | Synopsys Design Constraints (SDC) file. |
rtl | The folder that contains the design example synthesizable components. |
rtl/alt_mge_channel.v |
Design example DUT top-level files for the following Ethernet design examples:
|
rtl/alt_mge_multi_channel.sv |
Design example DUT top-level files for 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet design example. |
rtl/<Design Component> | The folder for each synthesizable component including Platform Designer generated IPs, such as LL 10GbE MAC, PHY, and FIFO. |
simulation/ed_sim/models | The folder that contains the testbench files. |
simulation/ed_sim/cadence simulation/ed_sim/mentor simulation/ed_sim/synopsys/vcs simulation/ed_sim/xcelium |
The folder that contains the simulation script. It also serves as a working area for the simulator. |
hwtesting/system_console_fm hwtesting/system_console |
The folder that contains system console scripts for hardware testing. All the required system console scripts are available in the folder system_console_fm. The folder system_console contains scripts that is only relevant to legacy devices. |