F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide

ID 720987
Date 11/29/2023
Public

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3.3.3. Reset Scheme

The global reset signal of the design example is asynchronous and active-high. Asserting this signal resets all channels and their components. Upon power-up, reset the design example (i_rst_n, i_tx_rst_n, and i_rx_rst_n).

Figure 10. Reset Scheme for 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example With and Without IEEE 1588v2 Feature (Reset is common for all instance)