ID
711009
Date
9/30/2024
Public
Visible to Intel only — GUID: fkd1636400185893
Ixiasoft
1. About the F-Tile Dynamic Reconfiguration Suite Core
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers
7. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide Archives
8. Document Revision History for the F-Tile Dynamic Reconfiguration Suite User Guide
4.1. Generating Dynamic Reconfiguration Design and Configuration Profiles
4.2. Dynamic Reconfiguration QSF Settings
4.3. Dynamic Reconfiguration Using QSF-driven Flow
4.4. Dynamic Reconfiguration Rules
4.5. Hardware States and Configuration Profiles
4.6. Nios® -Based Dynamic Reconfiguration Flow
4.7. Using the Tile Assignment Editor
4.8. Visualizing Dynamic Reconfiguration Group Placement
4.9. Assigning IP_COLOCATE Hierarchy
4.10. Example: Dynamic Reconfiguration with Multirate IP Flow
4.11. Example: Dynamic Reconfiguration Programming Sequence
4.12. Dynamic Reconfiguration Error Recovery Handling
4.13. Determining Profile Numbers
4.14. Master Clock Channel
4.15. Using the IP_RECONFIG_GROUP_PARENT QSF Assignment
4.16. Simulating the IP Core
6.1. Dynamic Reconfiguration New Trigger
6.2. Dynamic Reconfiguration Next Profile 0
6.3. Dynamic Reconfiguration Next Profile 1
6.4. Dynamic Reconfiguration Next Profile 2
6.5. Dynamic Reconfiguration Next Profile 3
6.6. Dynamic Reconfiguration Next Profile 4
6.7. Dynamic Reconfiguration Next Profile 5
6.8. Dynamic Reconfiguration Next Profile 6
6.9. Dynamic Reconfiguration Next Profile 7
6.10. Dynamic Reconfiguration Next Profile 8
6.11. Dynamic Reconfiguration Next Profile 9
6.12. Dynamic Reconfiguration Next Profile 10
6.13. Dynamic Reconfiguration Next Profile 11
6.14. Dynamic Reconfiguration Next Profile 12
6.15. Dynamic Reconfiguration Next Profile 13
6.16. Dynamic Reconfiguration Next Profile 14
6.17. Dynamic Reconfiguration Next Profile 15
6.18. Dynamic Reconfiguration Next Profile 16
6.19. Dynamic Reconfiguration Next Profile 17
6.20. Dynamic Reconfiguration Next Profile 18
6.21. Dynamic Reconfiguration Next Profile 19
6.22. Dynamic Reconfiguration Avalon MM Timeout
6.23. Dynamic Reconfiguration TX Channel Reconfiguration
6.24. Dynamic Reconfiguration RX Channel Reconfiguration
6.25. Dynamic Reconfiguration TX Channel in Reset Acknowledgment
6.26. Dynamic Reconfiguration TX Channel out of Reset
6.27. Dynamic Reconfiguration TX Channel Reset Control Init Status
6.28. Dynamic Reconfiguration TX Channel Source Alarm
6.29. Dynamic Reconfiguration RX Channel in Reset Acknowledgment
6.30. Dynamic Reconfiguration RX Channel out of Reset
6.31. Dynamic Reconfiguration RX Channel Reset Control Init Status
6.32. Dynamic Reconfiguration RX Channel Source Alarm
6.33. Dynamic Reconfiguration Local Error Status
Visible to Intel only — GUID: fkd1636400185893
Ixiasoft
1. About the F-Tile Dynamic Reconfiguration Suite Core
Updated for: |
---|
Intel® Quartus® Prime Design Suite 24.2 |
IP Version 10.0.0 |
The F-Tile Dynamic Reconfiguration Suite allows you to dynamically reconfigure a subset of the transceiver channels to operate in different modes, for example data rates, without impacting the adjacent active channels.
Depending on the protocol and hardware implementation, dynamic reconfiguration (DR) may reconfigure media access control (MAC), forward error correction (FEC), and physical coding sublayer (PCS) blocks, and the embedded multi-die interconnect bridges (EMIB). Additional dynamic reconfiguration features include:
- Setting up the required reference clocks. The system clock must be constant across all profiles in a selected dynamic reconfiguration group.
- Selecting the appropriate clocks input for each of the MAC, FEC, PCS, and transceiver blocks
- Setting the multiplexers to select the appropriate control and data path for MAC/PCS/PMA/FEC-direct modes
The FPGA IP products support the following dynamic reconfiguration flow:
- Nios® -based dynamic reconfiguration: This flow includes the inter protocol switching, such as Ethernet to CPRI protocols, and intra protocol link characteristic changes, such as CPRI data rate changes. A client application or an Quartus® Prime Nios® utility triggers the dynamic reconfiguration. When triggered, the Nios® performs the low level configuration register programming for various functional blocks.
This document describes the NIOS-based dynamic reconfiguration through the F-Tile Dynamic Reconfiguration Suite .
To perform dynamic reconfiguration (DR), you must first configure the F-Tile Dynamic Reconfiguration Suite and then the associated protocol IP. You can use the F-Tile CPRI PHY Multirate Intel FPGA IP Core, F-Tile Ethernet Multirate Intel FPGA IP core, and F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP core. You can also use the standard, single-rate IPs as well.