F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide

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ID 711009
Date 9/30/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile Dynamic Reconfiguration Suite Core 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers 7. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide Archives 8. Document Revision History for the F-Tile Dynamic Reconfiguration Suite User Guide
1. About the F-Tile Dynamic Reconfiguration Suite Core x
1.1. Features 1.2. Design Considerations 1.3. Device Family Support 1.4. Resource Utilization 1.5. Release Information
2. Interface Overview x
2.1. Clock Signals 2.2. Reset 2.3. Avalon® Memory-Mapped Interface 2.4. Control and Status Interface
4. Designing with the IP Core x
4.1. Generating Dynamic Reconfiguration Design and Configuration Profiles 4.2. Dynamic Reconfiguration QSF Settings 4.3. Dynamic Reconfiguration Using QSF-driven Flow 4.4. Dynamic Reconfiguration Rules 4.5. Hardware States and Configuration Profiles 4.6. Nios® -Based Dynamic Reconfiguration Flow 4.7. Using the Tile Assignment Editor 4.8. Visualizing Dynamic Reconfiguration Group Placement 4.9. Assigning IP_COLOCATE Hierarchy 4.10. Example: Dynamic Reconfiguration with Multirate IP Flow 4.11. Example: Dynamic Reconfiguration Programming Sequence 4.12. Dynamic Reconfiguration Error Recovery Handling 4.13. Determining Profile Numbers 4.14. Master Clock Channel 4.15. Using the IP_RECONFIG_GROUP_PARENT QSF Assignment 4.16. Simulating the IP Core
4.6. Nios® -Based Dynamic Reconfiguration Flow x
4.6.1. Selecting the Nios® Data Memory Size
4.7. Using the Tile Assignment Editor x
4.7.1. Creating QSF Assignments 4.7.2. Generating the IP_Colocate QSF Assignment
4.14. Master Clock Channel x
4.14.1. Selecting the Master Clock Channel
5. Block Description x
5.1. Clocks 5.2. Reset 5.3. Stack Clocking for Fracturability
6. Configuration Registers x
6.1. Dynamic Reconfiguration New Trigger 6.2. Dynamic Reconfiguration Next Profile 0 6.3. Dynamic Reconfiguration Next Profile 1 6.4. Dynamic Reconfiguration Next Profile 2 6.5. Dynamic Reconfiguration Next Profile 3 6.6. Dynamic Reconfiguration Next Profile 4 6.7. Dynamic Reconfiguration Next Profile 5 6.8. Dynamic Reconfiguration Next Profile 6 6.9. Dynamic Reconfiguration Next Profile 7 6.10. Dynamic Reconfiguration Next Profile 8 6.11. Dynamic Reconfiguration Next Profile 9 6.12. Dynamic Reconfiguration Next Profile 10 6.13. Dynamic Reconfiguration Next Profile 11 6.14. Dynamic Reconfiguration Next Profile 12 6.15. Dynamic Reconfiguration Next Profile 13 6.16. Dynamic Reconfiguration Next Profile 14 6.17. Dynamic Reconfiguration Next Profile 15 6.18. Dynamic Reconfiguration Next Profile 16 6.19. Dynamic Reconfiguration Next Profile 17 6.20. Dynamic Reconfiguration Next Profile 18 6.21. Dynamic Reconfiguration Next Profile 19 6.22. Dynamic Reconfiguration Avalon MM Timeout 6.23. Dynamic Reconfiguration TX Channel Reconfiguration 6.24. Dynamic Reconfiguration RX Channel Reconfiguration 6.25. Dynamic Reconfiguration TX Channel in Reset Acknowledgment 6.26. Dynamic Reconfiguration TX Channel out of Reset 6.27. Dynamic Reconfiguration TX Channel Reset Control Init Status 6.28. Dynamic Reconfiguration TX Channel Source Alarm 6.29. Dynamic Reconfiguration RX Channel in Reset Acknowledgment 6.30. Dynamic Reconfiguration RX Channel out of Reset 6.31. Dynamic Reconfiguration RX Channel Reset Control Init Status 6.32. Dynamic Reconfiguration RX Channel Source Alarm 6.33. Dynamic Reconfiguration Local Error Status
1. About the F-Tile Dynamic Reconfiguration Suite Core
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers
7. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide Archives
8. Document Revision History for the F-Tile Dynamic Reconfiguration Suite User Guide

8. Document Revision History for the F-Tile Dynamic Reconfiguration Suite User Guide

Document Version Quartus® Prime Version IP Version Changes
2024.10.04 24.2 10.0.0 Made the following changes:
  • Revised a note in Features section.
  • Corrected the following Avalon® Memory-Mapped Interface output signal names in Avalon® Memory-Mapped Interface :
    • o_dr_host_avmm_readdata
    • o_dr_host_avmm_readdata_valid
    • o_dr_host_avmm_waitrequest
  • Fixed the typo Save Time Assignment Editor to Save Tile Assignment Editor in Generating the IP_Colocate QSF Assignment.
2024.07.08 24.2 10.0.0 Updated the following Error Codes recovery description for the bit 23:16:
  • ERROR_CODE_2 = 8'h02
  • ERROR_CODE_9 = 8’h09
  • ERROR_CODE_23 = 8'h17
  • ERROR_CODE_24 = 8'h18
  • ERROR_CODE_29 = 8’h1D
2024.04.11 24.1 9.0.0 Made the following Changes:
  • Added Agilex™ 9 device family support in Device Family Support section.
  • Added QSF assignments to modify the PMA analog parameters in Dynamic Reconfiguration Using QSF-driven Flow.
  • In Dynamic Reconfiguration Error Recovery Handling topic, updated the Recovery enabled parameter default setting from Yes to NO.
  • Added Simulating the IP core topic.
2023.12.04 23.4 8.0.0
  • Updated resource utilization numbers due to changes from Nios® II to Nios® V
  • Added resource utilization for the following design example variants:
    • 25G Ethernet with PTP
    • 25G Ethernet to CPRI
    • 25G Ethernet to CPRI with 1G Ethernet
    • 100G Ethernet with PTP
    • 400G Ethernet with PTP
    • FHT 400G Ethernet
    • 400G PMA/FEC Direct PHY
  • In Clock Signals, updated i_cpu_clk signal description
  • In Control and Status Interface, added new o_dr_fast_sim_clk_sel signal
  • In Parameters, updated the F-Tile Dynamic Reconfiguration Suite figure
  • Changed the Recovery enabled parameter default setting from Yes to No.
2023.10.02 23.3 7.3.0
  • Revised the F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP figure and the F-Tile Dynamic Reconfiguration Suite Intel FPGA IP Parameters: Dynamic Reconfiguration Controller IP Tab table:
    • Removed Include NIOS parameter
    • Updated supported range values in NIOS data memory size parameter
  • Revised Master Clock Channel and Selecting the Master Clock Channel topics
  • Removed the IP master clock from the .qsf assignments in the following topics:
    • Dynamic Reconfiguration Using QSF-driven Flow
    • Creating QSF Assignments
    • Example: Dynamic Reconfiguration with Multirate IP Flow
  • Removed Automation for Selecting the Master Clock Channel
2023.07.03 23.2 7.2.0
  • Added 25G-1 PTP with RS-FEC (with 1GE PTP) for Ethernet to CPRI protocol in Features.
  • Added a note about ANLT is optional for Ethernet variants in Features.
  • Revised Design Considerations section.
  • Updated dyn_rcfg_local_error_stat_ctrl_reg field description in Dynamic Reconfiguration Local Error Status.
  • Added the following Error Codes in Dynamic Reconfiguration Local Error Status:
    • ERROR_CODE_23 = 8'h17
    • ERROR_CODE_24 = 8'h18
    • ERROR_CODE_28 = 8'h1C
2023.04.03 23.1 7.1.1
  • Added the following topics in Designing with the IP core chapter:
    • Dynamic Reconfiguration Error Recovery Handling
    • Automation for Selecting the Master Clock Channel
  • Added the following bit in the dyn_rcfg_local_error_stat_ctrl_reg field description table of Dynamic Reconfiguration Local Error Status.
    • 15:8
    • 7:5
    • 4:0
  • Updated IP version in Release information.
  • Added new content for Selecting the Nios® Data Memory Size.
  • Updated product family name to "Intel Agilex 7."
2022.12.19 22.4 7.1.0
  • Removed the following QSF settings and its description
    • set_instance_assignment -name IP_RECONFIG_GROUP_SHARED_SIP -to <ip_instance_hpath> ON|OFF in Dynamic Reconfiguration QSF Settings.
  • Added a note for i_cpu_clk clock signal in Clock Signals of Interface overview .
  • Added a note in dynamic reconfiguration flow diagram in Dynamic Reconfiguration Flow Facilitated by NIOS.
  • Added new sections:
    • Master Clock Channel
    • Selecting the Master Clock Channel
    • Using the IP_RECONFIG_PARENT Assignment.
  • Added the following in Dynamic Reconfiguration TX Channel Reconfiguration
    • TX Channels 0-3 : FHT channels 0-3
    • TX Channels 4-19: FGT channels 0-15
  • Added the following in Dynamic Reconfiguration RX Channel Reconfiguration
    • RX Channels 0-3 : FHT channels 0-3
    • RX Channels 4-19: FGT channels 0-15
  • Added new section: Dynamic Reconfiguration Local Error Status.
2022.09.26 22.3 7.0.0
  • Added the following base variants in Features.
    • FHT 400G-4 with RS-FEC for Ethernet
    • 25G-1 with RS-FEC for Ethernet to CPRI Protocol
  • Added a new topic: Ethernet to CPRI Design Example Parameters.
  • Added bullet about the usage of debug toolkit in Design Consideration.
  • Added new parameter: Recovery Enabled and screenshot in Parameter.
  • Added a note about IP_colocate is assigned on a "per IP" bases, not a "per profile" basis in Generating the IP_Colocate QSF Assignment.
  • Updated N =0-3: FHT channels 0-3 in the following chapters of Configuration Registers section:
    • Dynamic Reconfiguration TX Channel in Reset Acknowledgment
    • Dynamic Reconfiguration TX Channel out of Reset
    • Dynamic Reconfiguration TX Channel Reset Control Init Status
    • Dynamic Reconfiguration TX Channel Source Alarm
    • Dynamic Reconfiguration RX Channel in Reset Acknowledgment
    • Dynamic Reconfiguration RX Channel out of Reset
    • Dynamic Reconfiguration RX Channel Reset Control Init Status
    • Dynamic Reconfiguration RX Channel Source Alarm
2022.06.21 22.2 6.0.0
  • Added support for new design example variants:
    • Ethernet base variants:
      • 100G-4 with RS-FEC and PTP
      • 25G-1 with RS-FEC and PTP
      • 400G-8 with RS-FEC and PTP
    • PMA/FEC Direct PHY base variant: 400G-8 with RS-FEC
  • Added new sections:
    • Using the Tile Assignment Editor
    • Determining Profile Numbers
  • Corrected the access type of the following registers:
    • Dynamic Reconfiguration Next Profile 1
    • Dynamic Reconfiguration Next Profile 2
  • Corrected the bit offset of the following registers:
    • Dynamic Reconfiguration TX Channel Reconfiguration
    • Dynamic Reconfiguration TX Channel Reconfiguration
2022.04.22 22.1 5.0.0
  • Revised Features section.
  • Updated the 400G Ethernet and 50G PMA/FEC Direct PHY design example variants in the Resource Utilization.
  • Added PMA/FEC Direct PHY Multirate IP .qsf assignments in Dynamic Reconfiguration QSF Settings.
  • Added typical dynamic reconfiguration software flow in Nios-Based Dynamic Reconfiguration Flow.
  • Added new topics in the Designing with the IP Core chapter:
    • Dynamic Reconfiguration Using QSF-driven Flow
    • Dynamic Reconfiguration Rules
    • Selecting the Nios Data Memory Size
    • Visualizing Dynamic Reconfiguration Group Placement
    • Assigning IP_COLOCATE Hierarchy
    • Example: Dynamic Reconfiguration with Multirate IP Flow
    • Example: Dynamic Reconfiguration Programming Sequence
  • Globally removed FHT support.
2022.02.03 21.4 4.0.0 Initial release.
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