F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide

Download PDF
ID 711009
Date 4/11/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Core 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers 7. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide Archives 8. Document Revision History for the F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide
1. About the F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Core x
1.1. Features 1.2. Design Considerations 1.3. Device Family Support 1.4. Resource Utilization 1.5. Release Information
2. Interface Overview x
2.1. Clock Signals 2.2. Reset 2.3. Avalon® Memory-Mapped Interface 2.4. Control and Status Interface
4. Designing with the IP Core x
4.1. Generating Dynamic Reconfiguration Design and Configuration Profiles 4.2. Dynamic Reconfiguration QSF Settings 4.3. Dynamic Reconfiguration Using QSF-driven Flow 4.4. Dynamic Reconfiguration Rules 4.5. Hardware States and Configuration Profiles 4.6. Nios® -Based Dynamic Reconfiguration Flow 4.7. Using the Tile Assignment Editor 4.8. Visualizing Dynamic Reconfiguration Group Placement 4.9. Assigning IP_COLOCATE Hierarchy 4.10. Example: Dynamic Reconfiguration with Multirate IP Flow 4.11. Example: Dynamic Reconfiguration Programming Sequence 4.12. Dynamic Reconfiguration Error Recovery Handling 4.13. Determining Profile Numbers 4.14. Master Clock Channel 4.15. Using the IP_RECONFIG_GROUP_PARENT QSF Assignment 4.16. Simulating the IP Core
4.6. Nios® -Based Dynamic Reconfiguration Flow x
4.6.1. Selecting the Nios® Data Memory Size
4.7. Using the Tile Assignment Editor x
4.7.1. Creating QSF Assignments 4.7.2. Generating the IP_Colocate QSF Assignment
4.14. Master Clock Channel x
4.14.1. Selecting the Master Clock Channel
5. Block Description x
5.1. Clocks 5.2. Reset 5.3. Stack Clocking for Fracturability
6. Configuration Registers x
6.1. Dynamic Reconfiguration New Trigger 6.2. Dynamic Reconfiguration Next Profile 0 6.3. Dynamic Reconfiguration Next Profile 1 6.4. Dynamic Reconfiguration Next Profile 2 6.5. Dynamic Reconfiguration Next Profile 3 6.6. Dynamic Reconfiguration Next Profile 4 6.7. Dynamic Reconfiguration Next Profile 5 6.8. Dynamic Reconfiguration Next Profile 6 6.9. Dynamic Reconfiguration Next Profile 7 6.10. Dynamic Reconfiguration Next Profile 8 6.11. Dynamic Reconfiguration Next Profile 9 6.12. Dynamic Reconfiguration Next Profile 10 6.13. Dynamic Reconfiguration Next Profile 11 6.14. Dynamic Reconfiguration Next Profile 12 6.15. Dynamic Reconfiguration Next Profile 13 6.16. Dynamic Reconfiguration Next Profile 14 6.17. Dynamic Reconfiguration Next Profile 15 6.18. Dynamic Reconfiguration Next Profile 16 6.19. Dynamic Reconfiguration Next Profile 17 6.20. Dynamic Reconfiguration Next Profile 18 6.21. Dynamic Reconfiguration Next Profile 19 6.22. Dynamic Reconfiguration Avalon MM Timeout 6.23. Dynamic Reconfiguration TX Channel Reconfiguration 6.24. Dynamic Reconfiguration RX Channel Reconfiguration 6.25. Dynamic Reconfiguration TX Channel in Reset Acknowledgment 6.26. Dynamic Reconfiguration TX Channel out of Reset 6.27. Dynamic Reconfiguration TX Channel Reset Control Init Status 6.28. Dynamic Reconfiguration TX Channel Source Alarm 6.29. Dynamic Reconfiguration RX Channel in Reset Acknowledgment 6.30. Dynamic Reconfiguration RX Channel out of Reset 6.31. Dynamic Reconfiguration RX Channel Reset Control Init Status 6.32. Dynamic Reconfiguration RX Channel Source Alarm 6.33. Dynamic Reconfiguration Local Error Status
1. About the F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Core
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers
7. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide Archives
8. Document Revision History for the F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide

1.2. Design Considerations

  • A reconfiguration is only available within a specific topology. Reconfiguration across different topologies is not supported.
  • A reconfiguration is dependent on the fracturing rules specified in the F-Tile Architecture and PMA and FEC Direct PHY Intel® FPGA IP User Guide. For instance, you can separate a 200G fracture into two independent 100G fractures, and so on.
  • All switching must be done through a neutral state by asserting the digital data path reset and disabling the PMA.
  • Any configuration supports the SerDes rate reconfiguration provided that the rate is legal for a given serialization factor and consistent with any used system clock.
  • Dynamic reconfiguration for wireless IPs applies to TX and RX data paths in a symmetric manner.
  • PMA-direct supports equal PMA widths between TX and RX data paths. However, CPRI supports a PMA-direct width of 20-bit combined with a 32-bit PCS-direct width or 32-bit FEC+PCS-direct width.
  • All IPs supporting dynamic reconfiguration must adapt to the F-tile system clock. You cannot dynamically reconfigure the F-tile system PLLs, including reference clock pin and frequency.

  • The use of Debug Toolkits (NPDME, ETK, and TTK) may prevent successful Dynamic reconfiguration. Intel advises against the use of these Toolkits with protocol IP which is to be dynamically reconfigured.

  • An FGT protocol IP which has internal serial loopback enabled via the FGT Attribute access method must first disable serial loopback before performing a dynamic reconfiguration operation to the next target profile. Failure to disable internal serial loopback prior to a dynamic reconfiguration operation can result in the functional failure of the protocol IP.
  • Reconfiguration IDs are defined globally. These need to be unique per design, but not per tile. For example, if your design consists of two separate DR groups located in different tile locations, the reconfiguration ID values assigned to the two DR groups need to be unique. Overlapping of reconfiguration IDs for DR groups located in different tiles is not allowed.
  • Mixture of F-Tile FGT and FHT PMAs is not supported for "Exclusive" dynamic reconfiguration groups.
Related Information
Level Two Title