F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide

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ID 711009
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile Dynamic Reconfiguration Suite Core 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers 7. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide Archives 8. Document Revision History for the F-Tile Dynamic Reconfiguration Suite User Guide
1. About the F-Tile Dynamic Reconfiguration Suite Core x
1.1. Features 1.2. Design Considerations 1.3. Device Family Support 1.4. Resource Utilization 1.5. Release Information
2. Interface Overview x
2.1. Clock Signals 2.2. Reset 2.3. Avalon® Memory-Mapped Interface 2.4. Control and Status Interface
4. Designing with the IP Core x
4.1. Generating Dynamic Reconfiguration Design and Configuration Profiles 4.2. Dynamic Reconfiguration QSF Settings 4.3. Dynamic Reconfiguration Using QSF-driven Flow 4.4. Dynamic Reconfiguration Rules 4.5. Hardware States and Configuration Profiles 4.6. Nios® -Based Dynamic Reconfiguration Flow 4.7. Using the Tile Assignment Editor 4.8. Visualizing Dynamic Reconfiguration Group Placement 4.9. Assigning IP_COLOCATE Hierarchy 4.10. Example: Dynamic Reconfiguration with Multirate IP Flow 4.11. Example: Dynamic Reconfiguration Programming Sequence 4.12. Dynamic Reconfiguration Error Recovery Handling 4.13. Determining Profile Numbers 4.14. Master Clock Channel 4.15. Using the IP_RECONFIG_GROUP_PARENT QSF Assignment 4.16. Simulating the IP Core
4.6. Nios® -Based Dynamic Reconfiguration Flow x
4.6.1. Selecting the Nios® Data Memory Size
4.7. Using the Tile Assignment Editor x
4.7.1. Creating QSF Assignments 4.7.2. Generating the IP_Colocate QSF Assignment
4.14. Master Clock Channel x
4.14.1. Selecting the Master Clock Channel
5. Block Description x
5.1. Clocks 5.2. Reset 5.3. Stack Clocking for Fracturability
6. Configuration Registers x
6.1. Dynamic Reconfiguration New Trigger 6.2. Dynamic Reconfiguration Next Profile 0 6.3. Dynamic Reconfiguration Next Profile 1 6.4. Dynamic Reconfiguration Next Profile 2 6.5. Dynamic Reconfiguration Next Profile 3 6.6. Dynamic Reconfiguration Next Profile 4 6.7. Dynamic Reconfiguration Next Profile 5 6.8. Dynamic Reconfiguration Next Profile 6 6.9. Dynamic Reconfiguration Next Profile 7 6.10. Dynamic Reconfiguration Next Profile 8 6.11. Dynamic Reconfiguration Next Profile 9 6.12. Dynamic Reconfiguration Next Profile 10 6.13. Dynamic Reconfiguration Next Profile 11 6.14. Dynamic Reconfiguration Next Profile 12 6.15. Dynamic Reconfiguration Next Profile 13 6.16. Dynamic Reconfiguration Next Profile 14 6.17. Dynamic Reconfiguration Next Profile 15 6.18. Dynamic Reconfiguration Next Profile 16 6.19. Dynamic Reconfiguration Next Profile 17 6.20. Dynamic Reconfiguration Next Profile 18 6.21. Dynamic Reconfiguration Next Profile 19 6.22. Dynamic Reconfiguration Avalon MM Timeout 6.23. Dynamic Reconfiguration TX Channel Reconfiguration 6.24. Dynamic Reconfiguration RX Channel Reconfiguration 6.25. Dynamic Reconfiguration TX Channel in Reset Acknowledgment 6.26. Dynamic Reconfiguration TX Channel out of Reset 6.27. Dynamic Reconfiguration TX Channel Reset Control Init Status 6.28. Dynamic Reconfiguration TX Channel Source Alarm 6.29. Dynamic Reconfiguration RX Channel in Reset Acknowledgment 6.30. Dynamic Reconfiguration RX Channel out of Reset 6.31. Dynamic Reconfiguration RX Channel Reset Control Init Status 6.32. Dynamic Reconfiguration RX Channel Source Alarm 6.33. Dynamic Reconfiguration Local Error Status
1. About the F-Tile Dynamic Reconfiguration Suite Core
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers
7. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide Archives
8. Document Revision History for the F-Tile Dynamic Reconfiguration Suite User Guide

4.15. Using the IP_RECONFIG_GROUP_PARENT QSF Assignment

When you create hierarchical dynamic reconfiguration groups, you use the IP RECONFIG_GROUP_PARENT assignment. A typical use case is if you have several protocol IPs in different reconfiguration groups and want to establish a hierarchical relationship between these reconfiguration groups and an over-arching reconfiguration group.

The following example illustrates the Multirate PMA Direct protocol IP with an embedded IP_RECONFIG_GROUP_PARENT qsf assignment is specified in its .QIP file.
  • set_instance_assignment -entity mrip_directory_f_dr_201_pv6eoki -name IP_RECONFIG_GROUP%ip_instance_hpath%/RG_A_e -to U_base_profile|directphy_f_0

If you want to control two of these PMA Direct protocol IPs with a single Dynamic Reconfiguration Suite IP, you must first create an over-arching dynamic reconfiguration group, for example: TEST_GROUP.

Using the set_global_assignment -name example below:
  • set_global_assignment -name IP_RECONFIG_GROUP_TYPE "TEST_GROUP:INCLUSIVE:CLK_MASTER" -entity %entity_name%
To associate the individual Multirate IP dynamic reconfiguration groups with TEST_GROUP, make the following .qsf assignments:
  • set_global_assignment -name IP_RECONFIG_GROUP_PARENT "TEST_GROUP:%ip1_instance_hpath%|RG_A_E" -entity %entity_name%
  • set_global_assignment -name IP_RECONFIG_GROUP_PARENT "TEST_GROUP:%ip2_instance_hpath%/RG_A_E" -entity %entity_name%
The following assignments show the path for creating a specific design:
  • set_global_assignment -name IP_RECONFIG_GROUP_PARENT "TEST_GROUP:GENERATE_TRANSCEIVER_BLOCK[0].INSTX|GENERATE_PHY_DIRECT[0].MRIP_INST| DIRECTPHY_F_DR_0/RG_A_E" -entity devkit_demo
  • set_global_assignment -name IP_RECONFIG_GROUP_PARENT "TEST_GROUP:GENERATE_TRANSCEIVER_BLOCK[0].INSTX|GENERATE_PHY_DIRECT[1].MRIP_INST| DIRECTPHY_F_DR_0/RG_A_E" -entity devkit_demo

The .qsf file for the "Ethernet to CPRI" DR design example contains an additional example of how to use the IP_RECONFIG_GROUP_PARENT assignment.

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