F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide

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ID 711009
Date 9/30/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile Dynamic Reconfiguration Suite Core 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers 7. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide Archives 8. Document Revision History for the F-Tile Dynamic Reconfiguration Suite User Guide
1. About the F-Tile Dynamic Reconfiguration Suite Core x
1.1. Features 1.2. Design Considerations 1.3. Device Family Support 1.4. Resource Utilization 1.5. Release Information
2. Interface Overview x
2.1. Clock Signals 2.2. Reset 2.3. Avalon® Memory-Mapped Interface 2.4. Control and Status Interface
4. Designing with the IP Core x
4.1. Generating Dynamic Reconfiguration Design and Configuration Profiles 4.2. Dynamic Reconfiguration QSF Settings 4.3. Dynamic Reconfiguration Using QSF-driven Flow 4.4. Dynamic Reconfiguration Rules 4.5. Hardware States and Configuration Profiles 4.6. Nios® -Based Dynamic Reconfiguration Flow 4.7. Using the Tile Assignment Editor 4.8. Visualizing Dynamic Reconfiguration Group Placement 4.9. Assigning IP_COLOCATE Hierarchy 4.10. Example: Dynamic Reconfiguration with Multirate IP Flow 4.11. Example: Dynamic Reconfiguration Programming Sequence 4.12. Dynamic Reconfiguration Error Recovery Handling 4.13. Determining Profile Numbers 4.14. Master Clock Channel 4.15. Using the IP_RECONFIG_GROUP_PARENT QSF Assignment 4.16. Simulating the IP Core
4.6. Nios® -Based Dynamic Reconfiguration Flow x
4.6.1. Selecting the Nios® Data Memory Size
4.7. Using the Tile Assignment Editor x
4.7.1. Creating QSF Assignments 4.7.2. Generating the IP_Colocate QSF Assignment
4.14. Master Clock Channel x
4.14.1. Selecting the Master Clock Channel
5. Block Description x
5.1. Clocks 5.2. Reset 5.3. Stack Clocking for Fracturability
6. Configuration Registers x
6.1. Dynamic Reconfiguration New Trigger 6.2. Dynamic Reconfiguration Next Profile 0 6.3. Dynamic Reconfiguration Next Profile 1 6.4. Dynamic Reconfiguration Next Profile 2 6.5. Dynamic Reconfiguration Next Profile 3 6.6. Dynamic Reconfiguration Next Profile 4 6.7. Dynamic Reconfiguration Next Profile 5 6.8. Dynamic Reconfiguration Next Profile 6 6.9. Dynamic Reconfiguration Next Profile 7 6.10. Dynamic Reconfiguration Next Profile 8 6.11. Dynamic Reconfiguration Next Profile 9 6.12. Dynamic Reconfiguration Next Profile 10 6.13. Dynamic Reconfiguration Next Profile 11 6.14. Dynamic Reconfiguration Next Profile 12 6.15. Dynamic Reconfiguration Next Profile 13 6.16. Dynamic Reconfiguration Next Profile 14 6.17. Dynamic Reconfiguration Next Profile 15 6.18. Dynamic Reconfiguration Next Profile 16 6.19. Dynamic Reconfiguration Next Profile 17 6.20. Dynamic Reconfiguration Next Profile 18 6.21. Dynamic Reconfiguration Next Profile 19 6.22. Dynamic Reconfiguration Avalon MM Timeout 6.23. Dynamic Reconfiguration TX Channel Reconfiguration 6.24. Dynamic Reconfiguration RX Channel Reconfiguration 6.25. Dynamic Reconfiguration TX Channel in Reset Acknowledgment 6.26. Dynamic Reconfiguration TX Channel out of Reset 6.27. Dynamic Reconfiguration TX Channel Reset Control Init Status 6.28. Dynamic Reconfiguration TX Channel Source Alarm 6.29. Dynamic Reconfiguration RX Channel in Reset Acknowledgment 6.30. Dynamic Reconfiguration RX Channel out of Reset 6.31. Dynamic Reconfiguration RX Channel Reset Control Init Status 6.32. Dynamic Reconfiguration RX Channel Source Alarm 6.33. Dynamic Reconfiguration Local Error Status
1. About the F-Tile Dynamic Reconfiguration Suite Core
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers
7. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide Archives
8. Document Revision History for the F-Tile Dynamic Reconfiguration Suite User Guide

1.1. Features

Table 1.  Supported Design Example Variants
Protocol Base Variant Target Variants
CPRI 24G CPRI with RS-FEC 1.2G CPRI
2.4G CPRI
3G CPRI
4.9G CPRI
6G CPRI
9.8G CPRI
10G CPRI
10G CPRI with RS-FEC
12G CPRI
12G CPRI with RS-FEC
24G CPRI
24G CPRI with RS-FEC
Ethernet 100G-4 with RS-FEC 100G-4 with RS-FEC
100G-4
100G-2 with RS-FEC
2x50G-1 with RS-FEC
4x25G-1 with RS-FEC
4x25G-1
25G-1 with RS-FEC 25G-1 with RS-FEC
10G-1
400G-8 with RS-FEC 400G-8 with RS-FEC
2x200G-4 with RS-FEC
4x100G-2 with RS-FEC
100G-4 with RS-FEC and PTP 1 100G-4 with RS-FEC and PTP
100G-4 with PTP
100G-2 with RS-FEC and PTP
2x50G-1 with RS-FEC and PTP
4x25G-1 with RS-FEC and PTP
4x25G-1 with PTP
25G-1 with RS-FEC and PTP 2 25G-1 with RS-FEC and PTP
10G-1 with PTP
400G-8 with RS-FEC and PTP2 400G-8 with RS-FEC and PTP
2x200G-4 with RS-FEC and PTP
4x100G-2 with RS-FEC and PTP
FHT 400G-4 with RS-FEC FHT 400G-4 with RS-FEC
FHT 1x200G-4 with RS-FEC
FHT 2x200G-2 with RS-FEC
FHT 2x100G-2 with RS-FEC
FHT 4x100G-1 with RS-FEC
PMA/FEC Direct PHY 53.125G 53.125G
53.125G with RS-FEC
25.7815G
24.33024G
10.3125G
10.1376G
9.8304G
4.9152G
2.4576G
400G-8 with RS-FEC 1x400G-8 with RS-FEC (PAM4) FEC Direct (544,514)
2x200G-4 with RS-FEC (PAM4) FEC Direct (544,514)
2x100G-4 with RS-FEC (NRZ) FEC Direct (528,514)
Ethernet to CPRI 25G-1 with RS-FEC 25G-1 with RS-FEC
10G-1
24G CPRI with RS-FEC
10G CPRI
9.8G CPRI
4.9G CPRI
2.4G CPRI
25G-1 with RS-FEC (with 1GE) 25G-1 with RS-FEC
10G-1
1G-1
24G CPRI with RS-FEC
10G CPRI
9.8G CPRI
4.9G CPRI
2.4G CPRI

25G-1 PTP2 with RS-FEC (with 1GE PTP)

25G-1 with RS-FEC and PTP
10G-1 with PTP
1G-1 with PTP
24G CPRI with RS-FEC
10G CPRI
9.8G CPRI
4.9G CPRI
2.4G CPRI
Note: Ethernet variants support optional Auto-Negotiation and Link Training (AN/LT). However, it's important to note that updating from Ethernet IP with AN/LT enabled to CPRI IP, or vice versa, is not supported.
1 Basic Accuracy Mode
2 Advanced Accuracy Mode
Level Two Title