F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide

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ID 711009
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile Dynamic Reconfiguration Suite Core 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers 7. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide Archives 8. Document Revision History for the F-Tile Dynamic Reconfiguration Suite User Guide
1. About the F-Tile Dynamic Reconfiguration Suite Core x
1.1. Features 1.2. Design Considerations 1.3. Device Family Support 1.4. Resource Utilization 1.5. Release Information
2. Interface Overview x
2.1. Clock Signals 2.2. Reset 2.3. Avalon® Memory-Mapped Interface 2.4. Control and Status Interface
4. Designing with the IP Core x
4.1. Generating Dynamic Reconfiguration Design and Configuration Profiles 4.2. Dynamic Reconfiguration QSF Settings 4.3. Dynamic Reconfiguration Using QSF-driven Flow 4.4. Dynamic Reconfiguration Rules 4.5. Hardware States and Configuration Profiles 4.6. Nios® -Based Dynamic Reconfiguration Flow 4.7. Using the Tile Assignment Editor 4.8. Visualizing Dynamic Reconfiguration Group Placement 4.9. Assigning IP_COLOCATE Hierarchy 4.10. Example: Dynamic Reconfiguration with Multirate IP Flow 4.11. Example: Dynamic Reconfiguration Programming Sequence 4.12. Dynamic Reconfiguration Error Recovery Handling 4.13. Determining Profile Numbers 4.14. Master Clock Channel 4.15. Using the IP_RECONFIG_GROUP_PARENT QSF Assignment 4.16. Simulating the IP Core
4.6. Nios® -Based Dynamic Reconfiguration Flow x
4.6.1. Selecting the Nios® Data Memory Size
4.7. Using the Tile Assignment Editor x
4.7.1. Creating QSF Assignments 4.7.2. Generating the IP_Colocate QSF Assignment
4.14. Master Clock Channel x
4.14.1. Selecting the Master Clock Channel
5. Block Description x
5.1. Clocks 5.2. Reset 5.3. Stack Clocking for Fracturability
6. Configuration Registers x
6.1. Dynamic Reconfiguration New Trigger 6.2. Dynamic Reconfiguration Next Profile 0 6.3. Dynamic Reconfiguration Next Profile 1 6.4. Dynamic Reconfiguration Next Profile 2 6.5. Dynamic Reconfiguration Next Profile 3 6.6. Dynamic Reconfiguration Next Profile 4 6.7. Dynamic Reconfiguration Next Profile 5 6.8. Dynamic Reconfiguration Next Profile 6 6.9. Dynamic Reconfiguration Next Profile 7 6.10. Dynamic Reconfiguration Next Profile 8 6.11. Dynamic Reconfiguration Next Profile 9 6.12. Dynamic Reconfiguration Next Profile 10 6.13. Dynamic Reconfiguration Next Profile 11 6.14. Dynamic Reconfiguration Next Profile 12 6.15. Dynamic Reconfiguration Next Profile 13 6.16. Dynamic Reconfiguration Next Profile 14 6.17. Dynamic Reconfiguration Next Profile 15 6.18. Dynamic Reconfiguration Next Profile 16 6.19. Dynamic Reconfiguration Next Profile 17 6.20. Dynamic Reconfiguration Next Profile 18 6.21. Dynamic Reconfiguration Next Profile 19 6.22. Dynamic Reconfiguration Avalon MM Timeout 6.23. Dynamic Reconfiguration TX Channel Reconfiguration 6.24. Dynamic Reconfiguration RX Channel Reconfiguration 6.25. Dynamic Reconfiguration TX Channel in Reset Acknowledgment 6.26. Dynamic Reconfiguration TX Channel out of Reset 6.27. Dynamic Reconfiguration TX Channel Reset Control Init Status 6.28. Dynamic Reconfiguration TX Channel Source Alarm 6.29. Dynamic Reconfiguration RX Channel in Reset Acknowledgment 6.30. Dynamic Reconfiguration RX Channel out of Reset 6.31. Dynamic Reconfiguration RX Channel Reset Control Init Status 6.32. Dynamic Reconfiguration RX Channel Source Alarm 6.33. Dynamic Reconfiguration Local Error Status
1. About the F-Tile Dynamic Reconfiguration Suite Core
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers
7. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide Archives
8. Document Revision History for the F-Tile Dynamic Reconfiguration Suite User Guide

2.4. Control and Status Interface

Table 9.  Control and Status SignalsAll interface signals are clocked by the i_csr_clk clock.
Port Name Width (in bits) I/O Direction Description
o_dr_curr_profile_id 15 Output Specifies the selected profile.

The signal is only valid when o_dr_new_cfg_applied is 1.

You must decode the values to decide if the design is dynamically reconfigured.

o_dr_new_cfg_applied 1 Output Specifies the new configuration settings to the external logic, including tile CSRs, mux selection, etc.

Once the signal is sampled active, the external logic returns an acknowledgment to complete a full handshake signaling. Since this is a hardware action, the signal must complete within nanosecond ranges.

Once this signal is active, the Nios® continues to monitor the acknowledgment before proceeding to the next process in the dynamic reconfiguration flow. After an acknowledgment is sampled, this signal becomes inactive and the Nios® proceeds to the next step. If an acknowledgment is not sampled at a prolong period of time and time-out is enabled, this signal also becomes inactive and the Nios® proceeds to the next step at time-out. A time-out error also is signaled in this case.

i_dr_new_cfg_applied_ack 1 Input Specifies the full handshake acknowledgment in response to o_dr_new_cfg_applied signal.

The signal is active when set to 1.

o_dr_in_progress 1 Output Specifies that the dynamic reconfiguration is in progress.

This signal is active when set to 1.

o_dr_error_status 1 Output Specifies the overall dynamic reconfiguration SIP error status, including dynamically reconfigured Nios® firmware errors.

This signal is active when set to 1.
o_dr_fast_sim_clk_sel 1 Output Used during simulation only. When used, allows you to reduce the simulation run time by driving the i_cpu_clk port with different input frequencies.
  • When o_dr_fast_sim_clk_sel = 1: You can drive the i_cpu_clk port with a 100 GHz clock.
  • When o_dr_fast_sim_clk_sel = 0 and Enable ECC protection = OFF: You can drive the i_cpu_clk port with up to 250 MHz.
  • When o_dr_fast_sim_clk_sel = 0 and Enable ECC protection = ON: You can drive the i_cpu_clk port with up to 200 MHz.

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