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1.3. Generating the Design
Use the DisplayPort Intel® FPGA IP parameter editor in Quartus® Prime software to generate the design example.
Note: You need a Nios® V evaluation license. Refer to the Nios® V Processor Licensing topic in the Nios® V Embedded Processor Design Handbook.
Figure 3. Generating the Design Flow
- To generate an example design, follow these steps:
- For Quartus® Prime Pro Edition running in a Windows environment:
- Open " Nios® V Command Shell" from the Windows search path.
- Run "quartus" in Nios® V Command Shell to open Quartus® Prime Pro Edition.
- For Quartus® Prime Pro Edition running in a Linux environment:
- cd to <Quartus installation path>/niosv/bin and run "niosv-shell".
- Run "quartus" to open Quartus® Prime Pro Edition.
- For Quartus® Prime Pro Edition running in a Windows environment:
- Select Tools > IP Catalog, and select Agilex™ 7 F-Tile as the target device family.
Note: The design example only supports Agilex™ 7 F-Tile devices.
- In the IP Catalog, locate and double-click DisplayPort Intel FPGA IP. The New IP Variation window appears.
- Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.ip.
- Select an Agilex™ 7 F-Tile device in the Device field, or keep the default Quartus® Prime software device selection.
- Click OK. The parameter editor appears.
- Configure the desired parameters for both TX and RX.
Note: The Nios® V software has the capability to read and print out the DisplayPort Main Stream Attribute (MSA) information in the Nios® V terminal. To read or print the MSA information, turn on the Enable GPU Control parameter.
- Under the Design Example tab, select DisplayPort SST Parallel Loopback Without PCR, DisplayPort SST Parallel Loopback with AXIS Video Interface, DisplayPort SST TX-only, or DisplayPort SST RX-only.
- Select Synthesis to generate the hardware design example.
- For Target Development Kit, select Agilex™ 7 I-Series SoC Development Kit FA or Agilex™ 7 I-Series SoC Development Kit FB. This causes the target device selected in step 4 to change to match the device on the development kit.
- For Agilex™ 7 I-Series SoC Development Kit FA, the default device is AGIB027R31B1E1V.
- For Agilex™ 7 I-Series SoC Development Kit FB, the default device is AGIB027R31B1E1VAA.
- Click Generate Example Design.
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