Questa*-Intel® FPGA Edition Quick-Start: Intel® Quartus® Prime Pro Edition

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ID 691278
Date 6/26/2022
Public
Document Table of Contents
Document Table of Contents x
1. Questa*-Intel® FPGA Edition Quick-Start Intel® Quartus® Prime Pro Edition 2. Known Differences Between the Questa* Intel® FPGA Edition and ModelSim* - Intel® FPGA Edition 3. Questa*-Intel® FPGA Edition Simulation Quick-Start Intel® Quartus® Prime Pro Edition Revision History
1. Questa*-Intel® FPGA Edition Quick-Start Intel® Quartus® Prime Pro Edition x
1.1. Prerequisites 1.2. Open the Example Design 1.3. Specify EDA Tool Settings 1.4. Generate a Simulator Setup Script Template 1.5. Create the Simulation Script 1.6. Compile and Simulate the Design 1.7. View Signal Waveforms 1.8. Add Signals to the Simulation 1.9. Rerun Simulation
1. Questa*-Intel® FPGA Edition Quick-Start Intel® Quartus® Prime Pro Edition
2. Known Differences Between the Questa* Intel® FPGA Edition and ModelSim* - Intel® FPGA Edition
3. Questa*-Intel® FPGA Edition Simulation Quick-Start Intel® Quartus® Prime Pro Edition Revision History

1. Questa*-Intel® FPGA Edition Quick-Start Intel® Quartus® Prime Pro Edition

Updated for:
Intel® Quartus® Prime Design Suite 21.3
This document demonstrates how to simulate an Intel® Quartus® Prime Pro Edition design in the Questa*-Intel® FPGA Edition simulator.
Note: This document is prepared specifically with basic features to accommodate requirements to simulate the design example mentioned in Open the Example Design. If you intend to use a different use case with advanced features and you need more information to simulate your design, then refer to the Questa*-Intel® FPGA Edition documents from Siemens* available in the <installation directory>/questa_fe/docs/pdf_docs directory.

Design simulation verifies your design before device programming. Design simulation involves generating simulation files, compiling simulation models, running the simulation, and viewing the results. The following steps describe this flow:

  1. Prerequisites
    Both Questa* Intel® FPGA Edition and Questa* Intel® FPGA Starter Edition software require valid software licenses. However, the Questa* Intel® FPGA Starter Edition license is free.
  2. Open the Example Design
    The PLL_RAM example design includes Intel® FPGA IP cores to demonstrate the basic simulation flow. Perform the following steps to open the design example:
  3. Specify EDA Tool Settings
    Specify EDA tool settings to generate simulation files for supported simulators by performing the following steps:
  4. Generate a Simulator Setup Script Template
    Simulator setup scripts help you to simulate IP cores in your design. Follow these steps to generate the vendor-specific simulator setup script template for the IP modules in the example design. You can then customize this template for your specific simulation goals.
  5. Create the Simulation Script
    Create the simulation script to enable specific commands that simulate the IP cores in the project.
  6. Compile and Simulate the Design
    Run the top-level mentor_example.do script in the Questa*-Intel® FPGA Edition software to compile and simulate your design by performing the following steps:
  7. View Signal Waveforms
    Follow these steps to view signals in the testbench_1.v simulation waveform:
  8. Add Signals to the Simulation
    The CLOCK, WE, OFFSET, RESET_N, and RD_DATA signals automatically appear in the Wave window because the top-level design defines these I/O. In addition, you can optionally add internal signals to the simulation.
  9. Rerun Simulation
    You must rerun the simulation if you make changes to the simulation setup, such as adding signals to the Wave window, or modifying the testbench_1.v file. Follow these steps to rerun simulation:
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