DisplayPort Stratix® 10 FPGA IP Design Example User Guide

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ID 683887
Date 4/10/2024
Public
Document Table of Contents
Document Table of Contents x
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide 2. Parallel Loopback Design Examples 3. HDCP Over DisplayPort Design Example 4. DisplayPort Stratix® 10 FPGA IP Design Example User Guide Archives 5. Revision History for the DisplayPort Stratix® 10 FPGA IP Design Example User Guide
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. DisplayPort Intel® FPGA IP Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Regenerating ELF File
2. Parallel Loopback Design Examples x
2.1. Stratix® 10 DisplayPort SST Parallel Loopback Design Features 2.2. Stratix® 10 DisplayPort SST TX-only or RX-only Design Features 2.3. Design Components 2.4. Clocking Scheme 2.5. Interface Signals and Parameters 2.6. Hardware Setup 2.7. Simulation Testbench 2.8. DisplayPort Transceiver Reconfiguration Flow 2.9. Transceiver Lane Configurations
2.1. Stratix® 10 DisplayPort SST Parallel Loopback Design Features x
2.1.1. DisplayPort 2.0 UHBR10 (10 Gbps) Data Rate Support 2.1.2. DisplayPort 2.0 UHBR20 (20 Gbps) Data Rate Support 2.1.3. Enabling Adaptive Sync Support
2.2. Stratix® 10 DisplayPort SST TX-only or RX-only Design Features x
2.2.1. Stratix® 10 DisplayPort SST TX-only Design Features 2.2.2. Stratix® 10 DisplayPort SST RX-only Design Features
3. HDCP Over DisplayPort Design Example x
3.1. High-bandwidth Digital Content Protection (HDCP) 3.2. HDCP Over DisplayPort Design Example Architecture 3.3. Nios® V Processor Software Flow 3.4. Design Walkthrough 3.5. Protection of Encryption Key Embedded in FPGA Design 3.6. Debug Guidelines
3.4. Design Walkthrough x
3.4.1. Setting Up the Hardware 3.4.2. Generating the Design 3.4.3. Including HDCP Production Keys 3.4.4. Compiling the Design 3.4.5. Viewing the Results
3.4.3. Including HDCP Production Keys x
3.4.3.1. Storing Plain HDCP Production Keys in the FPGA (Support HDCP Key Management = 0) 3.4.3.2. Storing Encrypted HDCP Production Keys in the External Flash Memory or EEPROM (Support HDCP Key Management = 1)
3.4.3.1. Storing Plain HDCP Production Keys in the FPGA (Support HDCP Key Management = 0) x
3.4.3.1.1. HDCP Key Mapping from DCP Key Files 3.4.3.1.2. hdcp1x_tx_kmem.v and hdcp1x_rx_kmem.v files 3.4.3.1.3. hdcp2x_rx_kmem.v file 3.4.3.1.4. hdcp2x_tx_kmem.v file
3.4.3.2. Storing Encrypted HDCP Production Keys in the External Flash Memory or EEPROM (Support HDCP Key Management = 1) x
3.4.3.2.1. Intel KEYENC 3.4.3.2.2. Key Programmer
3.5. Protection of Encryption Key Embedded in FPGA Design x
3.5.1. Security Considerations
3.6. Debug Guidelines x
3.6.1. HDCP Status Signals 3.6.2. Modifying HDCP Software Parameters 3.6.3. Frequently Asked Questions (FAQ)
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. Parallel Loopback Design Examples
3. HDCP Over DisplayPort Design Example
4. DisplayPort Stratix® 10 FPGA IP Design Example User Guide Archives
5. Revision History for the DisplayPort Stratix® 10 FPGA IP Design Example User Guide

1.4. Simulating the Design

The DisplayPort Intel® FPGA IP design example testbench simulates a serial loopback design from a TX instance to an RX instance. An internal video pattern generator module drives the DisplayPort TX instance and the RX instance video output connects to CRC checkers in the testbench.
Figure 4. Design Simulation Flow
  1. Navigate to the simulation folder of your choice.
  2. Run the simulation script for the supported simulator. The script compiles and runs the testbench in the simulator.
  3. Analyze the results.
    Table 4.  Steps to Run Simulation
    Simulator Working Directory Instructions
    Riviera-PRO* /simulation/aldec
    In the command line, type 
    vsim -c -do aldec.do
    QuestaSim* /simulation/mentor
    In the command line, type 
    vsim -c -do mentor.do
    Xcelium* /simulation/xcelium
    In the command line, type 
    source xcelium.sh
    VCS* /simulation/synopsys/vcs
    In the command line, type 
    source vcs_sim.sh
    VCS* MX /simulation/synopsys/vcsmx
    In the command line, type 
    source vcsmx_sim.sh
    A successful simulation ends with the following message: 
    # SINK CRC_R = ac9c, CRC_G = ac9c, CRC_B = ac9c,
# SOURCE CRC_R = ac9c, CRC_G = ac9c, CRC_B = ac9c,
# Pass: Test Completed
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