PCB Stackup Design Considerations for Intel® FPGAs

Download PDF
ID 683883
Date 6/28/2017
Public
Document Table of Contents
Document Table of Contents x
1. PCB Stackup Design Considerations for Intel® FPGAs
1. PCB Stackup Design Considerations for Intel® FPGAs x
1.1. PCB Stackup Construction 1.2. Material Selection 1.3. Glass Transition Temperature 1.4. PCB Stackup Design 1.5. PCB Panelization 1.6. Conclusion 1.7. Specific Recommendations for Intel® FPGA Devices 1.8. References 1.9. Document Revision History
1.2. Material Selection x
1.2.1. Material Loss Considerations
1.2.1. Material Loss Considerations x
1.2.1.1. Relative Dielectric Constant 1.2.1.2. Loss Tangent 1.2.1.3. Fiberglass Weave Composition 1.2.1.4. Skin Effect
1.4. PCB Stackup Design x
1.4.1. Layer Count 1.4.2. Signal Layers 1.4.3. High Speed Signal Layer Planning 1.4.4. Power and Ground Layers 1.4.5. Power Plane and Capacitor Placement Strategy 1.4.6. Planar Capacitance and Spreading Inductance 1.4.7. Plane Layer Separation 1.4.8. Copper Weight 1.4.9. Hybrid Construction
1.4.5. Power Plane and Capacitor Placement Strategy x
1.4.5.1. General Rules for Capacitor and Power Plane Placement 1.4.5.2. Rules for Transceiver Power Plane Placement 1.4.5.3. Rules for High-Current Power Rails 1.4.5.4. Rules for PLL and Other Power Rails
1.7. Specific Recommendations for Intel® FPGA Devices x
1.7.1. Stratix® 10 Device Recommendations 1.7.2. Stratix® V Device Recommendations 1.7.3. Stratix IV Device Recommendations 1.7.4. Arria® 10 Device Recommendations 1.7.5. Arria® V Device Recommendations 1.7.6. Arria II Device Recommendations 1.7.7. Cyclone® 10 Device Recommendations 1.7.8. Cyclone® V Device Recommendations 1.7.9. Cyclone® IV Device Recommendations 1.7.10. Cyclone III Device Recommendations
1.7.1. Stratix® 10 Device Recommendations x
1.7.1.1. Stratix® 10 Device Family Power Plane Placement Example
1.7.2. Stratix® V Device Recommendations x
1.7.2.1. Stratix® V GX, GT, and GS Family Power Plane Placement Example 1.7.2.2. Stratix® V E Family Power Plane Placement Example 1.7.2.3. Stratix® V Transceiver Channel Breakout Recommendations
1.7.3. Stratix IV Device Recommendations x
1.7.3.1. Stratix IV GX and GT Family Power Plane Placement Example 1.7.3.2. Stratix IV E Family Power Plane Placement Example
1.7.4. Arria® 10 Device Recommendations x
1.7.4.1. Arria® 10 Device Family Power Plane Placement Example
1.7.5. Arria® V Device Recommendations x
1.7.5.1. Arria® V Device Family Power Plane Placement Example
1.7.6. Arria II Device Recommendations x
1.7.6.1. Arria II GX Family Power Plane Placement Example
1.7.7. Cyclone® 10 Device Recommendations x
1.7.7.1. Cyclone® 10 LP Device Family Power Plane Placement Example
1.7.8. Cyclone® V Device Recommendations x
1.7.8.1. Cyclone® V Device Family Power Plane Placement Example
1.7.9. Cyclone® IV Device Recommendations x
1.7.9.1. Cyclone® IV GX Family Power Plane Placement Example 1.7.9.2. Cyclone® IV E Family Power Plane Placement Example
1.7.10. Cyclone III Device Recommendations x
1.7.10.1. Cyclone III Family Power Plane Placement Example
1. PCB Stackup Design Considerations for Intel® FPGAs

1.4.2. Signal Layers

In high-density FPGAs, many signal layers are required to achieve full breakout of all available I/Os.

A good estimate for the minimum number of signal layers required is to count the depth of the row or column I/O signal balls of the FPGA device, divide that number by two, and round up to the nearest even whole number.

For example, on a Stratix IV GX device in an F1517 BGA package, the I/O row and column span 13 deep as shown in below figure. Therefore, a minimum of seven signal layers are required for a complete I/O signal breakout for that device. However, for a balanced PCB stackup, eight signals layers must be used.

Figure 4. BGA I/O Signal Depth

After the dedicated signal layers are determined, they must be arranged within the stackup. To maintain impedance control and provide a current return path, signal layers require an accompanying reference plane layer. Depending on whether microstrip or stripline topologies are used, several stackup construction choices are available.

Below figure (left) shows a microstrip construction. The Signal-Plane topology (S-P) places the signal layer on the surface of the PCB (either top or bottom) with a reference plane layer directly adjacent to the signal layer. With this topology, the difference between εr of air on one side and εr of the dielectric material on the other side causes odd and even mode trace velocity differences that result in far-end crosstalk in differential pair routing. One way to mitigate this situation when using microstrip routing is to use an embedded microstrip, where a thin layer of epoxy or soldermask is added over the surface traces to make εr more uniform, as shown in below figure (right).

Figure 5. Microstrip Signal Topologies

In a stripline construction, the single stripline topology uses Plane-Signal-Plane (P-S-P) to provide the best signal isolation but requires more layers for complete signal isolation. As a result, a more commonly used stripline construction is the dual stripline. This Plane-Signal-Signal-Plane (P-S-S-P) topology results in more efficient layer usage, but care must be observed to manage adjacent layer coupling. This coupling is usually reduced in the stackup design by increasing the adjacent signal-to-signal separation compared to the signal-to-plane separation. Doing this forces the majority of the return current along the reference plane layer directly above or below the signal instead of onto the adjacent signal layer. However, having large separations adds to the overall thickness of the board. This can impact standard board manufacturing if the aspect ratio of the via drill to board thickness is larger than 10:1. In addition to layer separation, signal-to-signal coupling can also be minimized by routing adjacent layers orthogonally to each other to minimize the overlapping coupling region. An added benefit of stripline routing is zero far-end crosstalk because of a uniform εr surrounding the signal traces.

Figure 6. Stripline Signal Topologies
Level Two Title