PCB Stackup Design Considerations for Intel® FPGAs

ID 683883
Date 6/28/2017
Public
Document Table of Contents

1.4.5.4. Rules for PLL and Other Power Rails

Follow these rules for placing the PLL and other power rails in an Intel® device:
  • PLL power rails should receive third priority in the power plane stackup. Typically, PLL power planes are located in the middle of the layer stack. As a result, the decoupling capacitors for these supplies can reside on either side of the PCB.
  • Place any remaining power rails where convenient in the layer stack and ensure sufficient decoupling capacitors are provided to adequately decouple the rail to meet its target impedance as determined by the Intel® PDN tool.