PCB Stackup Design Considerations for Intel® FPGAs

ID 683883
Date 6/28/2017
Public
Document Table of Contents

1.2.1. Material Loss Considerations

At low data rates, signal loss is caused mainly by impedance mismatches and less so by dielectric absorption and conductor losses from the material. Impedance mismatch is well understood by design engineers who regularly specify controlled impedance traces by tightly managing trace geometries, separation, and routes during the layout design. However, at data rates of 10 Gbps and above, material loss becomes very important and controlled dielectric construction must be considered during the design process. To mitigate loss caused by the material, the following material parameters must be considered during the material selection process:
  • Relative Dielectric Constant
  • Loss Tangent
  • Fiberglass Weave Composition
  • Skin Effect
These material parameters have significant impact on the electrical properties. Therefore, you should consider them as critical parameters during the stackup design.