AN 841: Signal Tap Tutorial for Intel® Stratix® 10 Partial Reconfiguration Design

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ID 683875
Date 5/07/2018
Public

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Document Table of Contents
Document Table of Contents x
1. Tutorial Overview 2. Tutorial Walkthrough 3. Tutorial Results 4. Document Revision History for AN 841: Signal Tap Tutorial for Intel® Stratix® 10 Partial Reconfiguration Design
1. Tutorial Overview x
1.1. PR Debug Considerations 1.2. Tutorial Software and Hardware Requirements 1.3. Tutorial Design Description 1.4. Downloading the Tutorial Design
1.4. Downloading the Tutorial Design x
1.4.1. Tutorial Design Files
2. Tutorial Walkthrough x
2.1. Step 1: Getting Started 2.2. Step 2: Preparing the Base Revision 2.3. Step 3: Preparing the Implementation Revisions for Debug 2.4. Step 4: Tapping Signals in the Implementation Persona 2.5. Step 5: Configuring Data Acquisition 2.6. Step 6: Setting Trigger Conditions 2.7. Step 7: Generating Programming Files 2.8. Step 8: Programming the Board 2.9. Step 9: Performing Data Acquisition
2.2. Step 2: Preparing the Base Revision x
2.2.1. Preparing the Static Region 2.2.2. Preparing the Default PR Persona
2.5. Step 5: Configuring Data Acquisition x
2.5.1. Add Acquisition Clock 2.5.2. Add Storage Parameters
3. Tutorial Results x
3.1. Waveforms for Slow Implementation 3.2. Waveforms for Default Implementation 3.3. Waveforms for Empty Implementation
1. Tutorial Overview
2. Tutorial Walkthrough
3. Tutorial Results
4. Document Revision History for AN 841: Signal Tap Tutorial for Intel® Stratix® 10 Partial Reconfiguration Design

1.3. Tutorial Design Description

The design for this tutorial consists of one 32-bit counter. At the board level, the design connects the clock to a 50MHz source, and connects the output to four LEDs on the FPGA. Selecting the output from the counter bits in a specific sequence causes the LEDs to blink at a specific frequency.
Figure 3. Flat Reference Design without PR Partitioning
Level Two Title