Intel® Arria® 10 CvP Initialization and Partial Reconfiguration over PCI Express User Guide

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ID 683871
Date 9/01/2020
Public
Document Table of Contents
Document Table of Contents x
1. CvP Initialization in Intel® Arria® 10 2. Design Considerations for CvP Initialization in Intel® Arria® 10 3. Understanding the Design Steps for CvP Initialization in Intel® Arria® 10 4. CvP Driver and Registers 5. Partial Reconfiguration over PCI Express in Intel® Arria® 10 6. Understanding Design Steps for PR over PCI Express in Intel® Arria® 10 7. Document Revision History for the Intel® Arria® 10 CvP Initialization and Partial Reconfiguration over PCI Express* User Guide
1. CvP Initialization in Intel® Arria® 10 x
1.1. Benefits of Using CvP 1.2. CvP System 1.3. CvP Support for Intel® Arria® 10 Devices 1.4. CvP Initialization 1.5. CvP Compression and Encryption Features 1.6. CvP Pins
2. Design Considerations for CvP Initialization in Intel® Arria® 10 x
2.1. Designing CvP for an Open System 2.2. Designing CvP for a Closed System
3. Understanding the Design Steps for CvP Initialization in Intel® Arria® 10 x
3.1. Generating the Synthesis HDL Files for Intel® Arria® 10 PCI Express IP Core 3.2. Setting up the CvP Parameters in Device and Pin Options 3.3. Compiling the Design 3.4. Splitting the SOF File 3.5. Bringing up the Hardware
3.5. Bringing up the Hardware x
3.5.1. Installing Jungo WinDriver in Windows Systems 3.5.2. Installing Jungo WinDriver in Linux Systems 3.5.3. Installing Open Source CvP Driver in Linux System 3.5.4. Modifying MSEL/DIP switch on Intel® Arria® 10 Dev-Kit 3.5.5. Programming CvP Images
4. CvP Driver and Registers x
4.1. CvP Driver Support 4.2. CvP Driver Flow 4.3. VSEC Registers for CvP
4.3. VSEC Registers for CvP x
4.3.1. Altera-defined Vendor Specific Capability Header Register 4.3.2. Altera-defined Vendor Specific Header Register 4.3.3. Altera Marker Register 4.3.4. CvP Status Register 4.3.5. CvP Mode Control Register 4.3.6. CvP Data Registers 4.3.7. CvP Programming Control Register 4.3.8. Uncorrectable Internal Error Status Register 4.3.9. Uncorrectable Internal Error Mask Register 4.3.10. Correctable Internal Error Status Register 4.3.11. Correctable Internal Error Mask Register
5. Partial Reconfiguration over PCI Express in Intel® Arria® 10 x
5.1. Benefits of Using PR over PCI Express 5.2. PR over PCIe System 5.3. Partial Reconfiguration Design Flow 5.4. Partial Reconfiguration IP Core
1. CvP Initialization in Intel® Arria® 10
2. Design Considerations for CvP Initialization in Intel® Arria® 10
3. Understanding the Design Steps for CvP Initialization in Intel® Arria® 10
4. CvP Driver and Registers
5. Partial Reconfiguration over PCI Express in Intel® Arria® 10
6. Understanding Design Steps for PR over PCI Express in Intel® Arria® 10
7. Document Revision History for the Intel® Arria® 10 CvP Initialization and Partial Reconfiguration over PCI Express* User Guide

3.2. Setting up the CvP Parameters in Device and Pin Options

Follow these steps to specify CvP parameters:

  1. On the Quartus Prime Assignments menu, select Device, and then click Device and Pin Options.
  2. Under Category select General, and then enable the following option:
    1. Auto-restart configuration after error, enable this option to allow automatic restart of configuration attempts if an error is detected. Any restarted configuration may exceed the required PCIe startup time to allow bus enumeration and prevent the use of quartus_cvp for core programming.
    Leave all other options disabled.
  3. Under Category, select CvP Settings, and specify the following settings:
    Parameter Value
    Configuration via Protocol Core initialization
    Enable CvP_CONFDONE pin Turn this option on.
    Enable open drain on CvP_CONFDONE pin Turn this option on.
    Figure 6. Illustrating the specified CvP parameters in Device and Pin options dialog box
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