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1. CvP Initialization in Intel® Arria® 10
2. Design Considerations for CvP Initialization in Intel® Arria® 10
3. Understanding the Design Steps for CvP Initialization in Intel® Arria® 10
4. CvP Driver and Registers
5. Partial Reconfiguration over PCI Express in Intel® Arria® 10
6. Understanding Design Steps for PR over PCI Express in Intel® Arria® 10
7. Document Revision History for the Intel® Arria® 10 CvP Initialization and Partial Reconfiguration over PCI Express* User Guide
4.3.1. Altera-defined Vendor Specific Capability Header Register
4.3.2. Altera-defined Vendor Specific Header Register
4.3.3. Altera Marker Register
4.3.4. CvP Status Register
4.3.5. CvP Mode Control Register
4.3.6. CvP Data Registers
4.3.7. CvP Programming Control Register
4.3.8. Uncorrectable Internal Error Status Register
4.3.9. Uncorrectable Internal Error Mask Register
4.3.10. Correctable Internal Error Status Register
4.3.11. Correctable Internal Error Mask Register
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3.1. Generating the Synthesis HDL Files for Intel® Arria® 10 PCI Express IP Core
Follow these steps to generate the synthesis HDL files with CvP enabled:.
- On the Tools menu, select Platform Designer .
- Open .qsys file of the project.
- On the System Contents tab, right-click Intel® Arria® 10 Hard IP for PCI Express and select Edit.
- Under System Settings, turn on Enable Configuration via Protocol as shown in the following figure:
Figure 5. Illustrating the specified option in Systems Setting dialog box
- Click Finish.
- On the Generation tab, specify your parameters to generate RTL. Then click Generate at the bottom of the window.
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