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1. CvP Initialization in Intel® Arria® 10
2. Design Considerations for CvP Initialization in Intel® Arria® 10
3. Understanding the Design Steps for CvP Initialization in Intel® Arria® 10
4. CvP Driver and Registers
5. Partial Reconfiguration over PCI Express in Intel® Arria® 10
6. Understanding Design Steps for PR over PCI Express in Intel® Arria® 10
7. Document Revision History for the Intel® Arria® 10 CvP Initialization and Partial Reconfiguration over PCI Express* User Guide
4.3.1. Altera-defined Vendor Specific Capability Header Register
4.3.2. Altera-defined Vendor Specific Header Register
4.3.3. Altera Marker Register
4.3.4. CvP Status Register
4.3.5. CvP Mode Control Register
4.3.6. CvP Data Registers
4.3.7. CvP Programming Control Register
4.3.8. Uncorrectable Internal Error Status Register
4.3.9. Uncorrectable Internal Error Mask Register
4.3.10. Correctable Internal Error Status Register
4.3.11. Correctable Internal Error Mask Register
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3.5.4. Modifying MSEL/DIP switch on Intel® Arria® 10 Dev-Kit
The MSEL/DIP switch labeled SW5 on the back of the Intel® Arria® 10 FPGA Development Kit. The right position signifies logic zero and the left position signifies logic one. For example, to set the MSEL [2:0] = 011 follow the sequence as left, left, right from top to bottom.
Configuration Scheme | VCCPGM (V) | Power-On Reset (POR) Delay | Valid MSEL[2..0] |
---|---|---|---|
JTAG-based configuration | — | — | Use any valid MSEL pin settings below |
AS (x1 and x4) | 1.8 | Fast | 010 |
Standard | 011 | ||
PS and FPP (x8, x16, and x32) |
1.2/1.5/1.8 | Fast | 000 |
Standard | 001 |