Intel® Arria® 10 CvP Initialization and Partial Reconfiguration over PCI Express User Guide

ID 683871
Date 9/01/2020
Public
Document Table of Contents

7. Document Revision History for the Intel® Arria® 10 CvP Initialization and Partial Reconfiguration over PCI Express* User Guide

Date Changes
2020.09.01
  • Added information about custom CvP driver for Linux in section Bringing Up the Hardware.
  • Added a note about the availability of Jungo WinDriver in the following sections:
    • Bringing Up the Hardware
    • CvP Driver Support
  • Added new section Installing Open Source CvP Driver in Linux System.
  • Added steps to program the core image using the open source Linux driver in section Programming CvP Images.
2019.10.11
  • Added a command to generate CvP periphery image (.jam) file for the JTAG configuration in section Splitting the SOF File.
  • Clarified the use *.pof file for the Passive Serial or Fast Passive Serial configuration mode.
  • Implemented Intel rebranding.
2019.04.12 Corrected the Figure: PCIe Timing Sequence in CvP Initialization Mode for link training state.
2016.10.31
  • Changed the document title from 'Arria CvP Initialization and Partial Reconfiguration via Protocol User Guide' to 'Arria CvP Initialization and Partial Reconfiguration over PCI Express User Guide'.
  • Removed the topic Autonomous Mode, instead refer to the Intel® Arria® 10 Avalon-MM/ST Interface for PCIe Solutions User Guide.
  • Added the pin descriptions for INIT_DONE and CONF_DONE.
  • Corrected the PCIe Timing Sequence diagram for CvP initialization.
  • Added the timeout value for CvP_CONFIG_READY in the Figure: CvP Driver Flow.
  • Added the topic Partial Reconfiguration Design Flow to the Chapter: Partial Reconfiguration over Protocol in Intel® Arria® 10 .
  • Removed the Design Planning for PR over PCI Express in Intel® Arria® 10 chapter. Instead refer to Creating a Partial Reconfiguration Design.
  • Removed the following topics from Chapter: Understanding Design Steps for PR over PCI Express in Intel® Arria® 10 :
    • Creating a Qsys design
    • Creating User Logic and Top Level File
    • Creating PR Partition
    • Generating Base SOF/RBF Bitstreams
    • Creating PR Revision
    • Generating PR Bitstreams
    • Bringing Up the Hardware
  • Fixed assorted typos and formatting issues.
2016.05.02 Initial release