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1. CvP Initialization in Intel® Arria® 10
2. Design Considerations for CvP Initialization in Intel® Arria® 10
3. Understanding the Design Steps for CvP Initialization in Intel® Arria® 10
4. CvP Driver and Registers
5. Partial Reconfiguration over PCI Express in Intel® Arria® 10
6. Understanding Design Steps for PR over PCI Express in Intel® Arria® 10
7. Document Revision History for the Intel® Arria® 10 CvP Initialization and Partial Reconfiguration over PCI Express* User Guide
4.3.1. Altera-defined Vendor Specific Capability Header Register
4.3.2. Altera-defined Vendor Specific Header Register
4.3.3. Altera Marker Register
4.3.4. CvP Status Register
4.3.5. CvP Mode Control Register
4.3.6. CvP Data Registers
4.3.7. CvP Programming Control Register
4.3.8. Uncorrectable Internal Error Status Register
4.3.9. Uncorrectable Internal Error Mask Register
4.3.10. Correctable Internal Error Status Register
4.3.11. Correctable Internal Error Mask Register
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5. Partial Reconfiguration over PCI Express in Intel® Arria® 10
Partial reconfiguration (PR) is an advanced feature which allows you to reconfigure a portion of the FPGA design’s core logic dynamically, whilst the remainder of the FPGA device continues to operate. Partial reconfiguration is supported in Cyclone® V 2, Stratix® V, and Intel® Arria® 10 device families. Partial Reconfiguration over Protocol offers a solution for configuring the FPGA fabric through the PCI Express (PCIe) link.
Note: For Intel® Arria® 10 devices, you need the Intel® Quartus® Prime Pro Edition software to utilize the advanced features like partial reconfiguration.
2 The partial reconfiguration feature is available for Cyclone® V E, GX, SE, and SX devices with the "SC" suffix in their part number.