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1. CvP Initialization in Intel® Arria® 10
2. Design Considerations for CvP Initialization in Intel® Arria® 10
3. Understanding the Design Steps for CvP Initialization in Intel® Arria® 10
4. CvP Driver and Registers
5. Partial Reconfiguration over PCI Express in Intel® Arria® 10
6. Understanding Design Steps for PR over PCI Express in Intel® Arria® 10
7. Document Revision History for the Intel® Arria® 10 CvP Initialization and Partial Reconfiguration over PCI Express* User Guide
4.3.1. Altera-defined Vendor Specific Capability Header Register
4.3.2. Altera-defined Vendor Specific Header Register
4.3.3. Altera Marker Register
4.3.4. CvP Status Register
4.3.5. CvP Mode Control Register
4.3.6. CvP Data Registers
4.3.7. CvP Programming Control Register
4.3.8. Uncorrectable Internal Error Status Register
4.3.9. Uncorrectable Internal Error Mask Register
4.3.10. Correctable Internal Error Status Register
4.3.11. Correctable Internal Error Mask Register
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5.4. Partial Reconfiguration IP Core
PR over PCIe is performed using the PR IP core as an internal host residing in the core logic, which automatically instantiates the corresponding crcblock and prblock WYSIWYG atom primitives.
Figure 13. PR IP Core as an Internal Host
During partial reconfiguration, the PR Control Block (CB) is in Passive Parallel x16 or x32 programming mode.
Figure 14. PR IP Core Components
When you instantiate the PR IP core, the Main Controller module which includes the Control Block Interface Controller, Freeze/Unfreeze Controller, and the Data Source Controller are all instantiated. A Data Source Interface module provides you with a JTAG Debug Interface and PR Data Interface.