Intel® Arria® 10 CvP Initialization and Partial Reconfiguration over PCI Express User Guide

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ID 683871
Date 9/01/2020
Public
Document Table of Contents
Document Table of Contents x
1. CvP Initialization in Intel® Arria® 10 2. Design Considerations for CvP Initialization in Intel® Arria® 10 3. Understanding the Design Steps for CvP Initialization in Intel® Arria® 10 4. CvP Driver and Registers 5. Partial Reconfiguration over PCI Express in Intel® Arria® 10 6. Understanding Design Steps for PR over PCI Express in Intel® Arria® 10 7. Document Revision History for the Intel® Arria® 10 CvP Initialization and Partial Reconfiguration over PCI Express* User Guide
1. CvP Initialization in Intel® Arria® 10 x
1.1. Benefits of Using CvP 1.2. CvP System 1.3. CvP Support for Intel® Arria® 10 Devices 1.4. CvP Initialization 1.5. CvP Compression and Encryption Features 1.6. CvP Pins
2. Design Considerations for CvP Initialization in Intel® Arria® 10 x
2.1. Designing CvP for an Open System 2.2. Designing CvP for a Closed System
3. Understanding the Design Steps for CvP Initialization in Intel® Arria® 10 x
3.1. Generating the Synthesis HDL Files for Intel® Arria® 10 PCI Express IP Core 3.2. Setting up the CvP Parameters in Device and Pin Options 3.3. Compiling the Design 3.4. Splitting the SOF File 3.5. Bringing up the Hardware
3.5. Bringing up the Hardware x
3.5.1. Installing Jungo WinDriver in Windows Systems 3.5.2. Installing Jungo WinDriver in Linux Systems 3.5.3. Installing Open Source CvP Driver in Linux System 3.5.4. Modifying MSEL/DIP switch on Intel® Arria® 10 Dev-Kit 3.5.5. Programming CvP Images
4. CvP Driver and Registers x
4.1. CvP Driver Support 4.2. CvP Driver Flow 4.3. VSEC Registers for CvP
4.3. VSEC Registers for CvP x
4.3.1. Altera-defined Vendor Specific Capability Header Register 4.3.2. Altera-defined Vendor Specific Header Register 4.3.3. Altera Marker Register 4.3.4. CvP Status Register 4.3.5. CvP Mode Control Register 4.3.6. CvP Data Registers 4.3.7. CvP Programming Control Register 4.3.8. Uncorrectable Internal Error Status Register 4.3.9. Uncorrectable Internal Error Mask Register 4.3.10. Correctable Internal Error Status Register 4.3.11. Correctable Internal Error Mask Register
5. Partial Reconfiguration over PCI Express in Intel® Arria® 10 x
5.1. Benefits of Using PR over PCI Express 5.2. PR over PCIe System 5.3. Partial Reconfiguration Design Flow 5.4. Partial Reconfiguration IP Core
1. CvP Initialization in Intel® Arria® 10
2. Design Considerations for CvP Initialization in Intel® Arria® 10
3. Understanding the Design Steps for CvP Initialization in Intel® Arria® 10
4. CvP Driver and Registers
5. Partial Reconfiguration over PCI Express in Intel® Arria® 10
6. Understanding Design Steps for PR over PCI Express in Intel® Arria® 10
7. Document Revision History for the Intel® Arria® 10 CvP Initialization and Partial Reconfiguration over PCI Express* User Guide

3.5.5. Programming CvP Images

You must program the periphery image (.periph.jic) if you are using Active Serial mode and then download the core image (.core.rbf) using the PCIe Link. You can use JTAG to load different programming files (i.e. .sof/.jic/periph.pof) into your selected CvP initialization enabled Intel® Arria® 10 device.

After loading the periphery image via the JTAG port, the link should reach the expected data rate and link width. You can confirm the PCIe link status using the RW Utilities.

Follow these steps to program and test the CvP functionality:
  1. Plug the Intel® Arria® 10 FPGA Development Kit into the PCI Express slot of the DUT PC and power it ON. Altera recommends that you use the ATX power supply that the development kit includes.
  2. On the host PC, open the Quartus Prime Tools menu and select Programmer.
  3. Click Auto Detect to verify that the USB Blaster recognizes the Intel® Arria® 10 FPGA.
  4. Follow these steps to program the periphery image:
    1. Select Intel® Arria® 10 device, and then right click None under File column.
    2. Navigate to .periph.jic file and click Open.
    3. Under Program/Configure column, select the respective devices. For example, 10AX115S1E2 and EPCQL1024.
    4. Click start to program the periphery image into EPCQL1024 flash.
    Figure 8. Illustrating the specified options to the program periphery image
  5. After the .periph.jic is programmed, the FPGA must be powered cycle to allow the new peripheral image to load from the on-board flash into the FPGA. To force the host PC to re-enumerate the link with the new image, power cycle the DUT PC and the Intel® Arria® 10 FPGA Development Kit.
  6. You can use RW Utilities or another system software driver to verify the link status. You can also confirm expected link speed and width.
  7. Follow these steps to program the core image:
    1. Copy the .core.rbf file to appropriate Quartus Prime bin install directory. Depending on the 32-bit or 64-bit system, the folder is …./quartus/bin32 or …./quartus/bin64.
    2. Open a Command Prompt in Windows, change the directory to the same mentioned above where the file is copied.
    3. Type the following command to program the core image:

      quartus_cvp --vid=<Vendor ID> --did=<Device ID> xxx.core.rbf

      where the value of Vendor ID and Device ID are in hexadecimal and specified in the Hard IP for PCI Express dialog box. For example, quartus_cvp --vid=1172 --did=e003 xxx.core.rbf.

    4. The figure below shows the results of a successful CvP programming.
      Figure 9. Command Prompt Console
    If you implement your own software driver to program the core image, refer to the CvP Driver Support section.
    If you are using the open source Linux driver, perform the following steps to program the core image:
    1. Copy the .core.rbf file to your working directory.
    2. Open a console in Linux. Change directory to the same mentioned above where the file is copied.
    3. Program the core image by typing the following command:
      cp *.core.rbf /dev/altera_cvp
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