Agilex™ 7 Device Family High-Speed Serial Interface Signal Integrity Design Guidelines

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ID 683864
Date 11/20/2024
Public
Document Table of Contents
Document Table of Contents x
1. Signal Integrity (SI) in High-Speed PCB Designs
1. Signal Integrity (SI) in High-Speed PCB Designs x
1.1. Supported Protocols 1.2. Channel Insertion Loss (IL) Budget Calculation 1.3. PCB Materials and Stackup Design Guidelines 1.4. PCB Design Guidelines 1.5. Document Revision History for the Agilex™ 7 Device Family High-Speed Serial Interface Signal Integrity Design Guidelines
1.3. PCB Materials and Stackup Design Guidelines x
1.3.1. Mitigating Insertion Loss with Dielectric Material 1.3.2. Power Layers 1.3.3. Reference Planes 1.3.4. Layer Assignment 1.3.5. Impedance 1.3.6. Via Drill Size 1.3.7. Fiber Weave 1.3.8. Reference Stackup
1.4. PCB Design Guidelines x
1.4.1. General PCB Design Guidelines 1.4.2. E-Tile PCB Design Guidelines 1.4.3. F-Tile PCB Design Guidelines 1.4.4. P-Tile PCB Design Guidelines 1.4.5. R-Tile PCB Guidelines
1.4.1. General PCB Design Guidelines x
1.4.1.1. PCB Traces 1.4.1.2. PCB Vias 1.4.1.3. Connector Breakout 1.4.1.4. AC Coupling Capacitor 1.4.1.5. Others
1.4.3. F-Tile PCB Design Guidelines x
1.4.3.1. F-Tile Features and Capabilities 1.4.3.2. Optimizing the Passive Channel 1.4.3.3. COM Simulations 1.4.3.4. Simulating the Active Channel
1.4.5. R-Tile PCB Guidelines x
1.4.5.1. R-Tiles Features and Capabilities 1.4.5.2. R-Tile Design Layout Examples 1.4.5.3. Landing Pad Cut-out Optimization of AC Coupling Capacitor 1.4.5.4. R-tile HSSI Breakout Routing in BGA Area and MCIO connector Pin Area 1.4.5.5. AC Coupling Capacitor Placement Around MCIO Connector 1.4.5.6. PCIe Gen5 Add-in Card Edge Finger Breakout Design Guidelines
1. Signal Integrity (SI) in High-Speed PCB Designs

1.4.4. P-Tile PCB Design Guidelines

  • For PCIe* add-in-card designs, the insertion loss from the top of the edge finger to the silicon pad (including the package insertion loss and the silicon loss) for both the receiver and transmitter paths must not exceed 8 dB at 8 GHz. Because the P-tile package plus silicon loss is under 3 dB at 8GHZ, you may have an add-in-card PCB loss under 5 dB at 8GHZ.
  • Use an insertion loss of 28 dB at 8GHZ including the transmitter and receiver packages as the reference maximum loss for end-to-end channel design, but validate the final design through complete channel simulation and measurements.
  • Use a trace impedance of 85 Ω for P-tile differential channels.
  • Intra pair skew: ±1 mil
  • Make via stubs as short as possible. Altera recommends using back-drill to shorten the via stub and control the stub lengths of less than 30 mils.
  • Use additional ground reference vias for the package edge differential pairs in order to keep ground reference via symmetry for the two signal vias that comprise a differential pair.
  • Place the AC coupling capacitors on FPGA TX paths close to the FPGA or connector. Do not place them in the middle of the trace routing.
  • Optimize the PCIe* slot connector footprint by cutting the ground planes beneath the connector PCB pad, considering the interaction of the connector pin and PCB pad, for less return loss.
  • Ensure that the PCIe* slot connector high-speed signal pin breakout is at the periphery of the connector as shown below to avoid a long stub caused by the connector pin and PCB pad as shown in figure PCIe* Slot Connector and PCB Pad Connection and figure PCIe* Slot Connector Breakout.
Figure 24.  PCIe* Slot Connector and PCB Pad Connection
Figure 25.  PCIe* Slot Connector Breakout
  • For an add-in card that supports PCIe* Gen4 16.0 GT/s, make sure that there are no inner-layer conductors of any kind, including ground or power planes, beneath the edge-fingers (for a distance of 15 mils). You may add inner plane layers beneath any of the edge fingers if they extend no more than 2 mm into the edge finger region from the main routing area of the board and are at a depth of at least 15 mils (0.38 mm) beneath the edge finger copper pads on the surface of the PCB as shown in figure Add-in Card Edge-finger Regions with Allowed Inner Layer Plane Volume Indicated.
Figure 26. Add-in Card Edge-finger Regions with Allowed Inner Layer Plane Volume Indicated
  • For add-in-card ground fingers, make sure that the distance between a horizontal line across the top edge ground fingers and a horizontal line across the bottom edge of the ground via pads does not exceed 15 mils. Also join the adjacent ground edge-fingers at the lowered via location to provide additional improvement in the ground resonance as shown Add-in-card Ground Finger Layout.
Figure 27. Add-in-card Ground Finger Layout
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