Agilex™ 7 Device Family High-Speed Serial Interface Signal Integrity Design Guidelines

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ID 683864
Date 11/20/2024
Public
Document Table of Contents
Document Table of Contents x
1. Signal Integrity (SI) in High-Speed PCB Designs
1. Signal Integrity (SI) in High-Speed PCB Designs x
1.1. Supported Protocols 1.2. Channel Insertion Loss (IL) Budget Calculation 1.3. PCB Materials and Stackup Design Guidelines 1.4. PCB Design Guidelines 1.5. Document Revision History for the Agilex™ 7 Device Family High-Speed Serial Interface Signal Integrity Design Guidelines
1.3. PCB Materials and Stackup Design Guidelines x
1.3.1. Mitigating Insertion Loss with Dielectric Material 1.3.2. Power Layers 1.3.3. Reference Planes 1.3.4. Layer Assignment 1.3.5. Impedance 1.3.6. Via Drill Size 1.3.7. Fiber Weave 1.3.8. Reference Stackup
1.4. PCB Design Guidelines x
1.4.1. General PCB Design Guidelines 1.4.2. E-Tile PCB Design Guidelines 1.4.3. F-Tile PCB Design Guidelines 1.4.4. P-Tile PCB Design Guidelines 1.4.5. R-Tile PCB Guidelines
1.4.1. General PCB Design Guidelines x
1.4.1.1. PCB Traces 1.4.1.2. PCB Vias 1.4.1.3. Connector Breakout 1.4.1.4. AC Coupling Capacitor 1.4.1.5. Others
1.4.3. F-Tile PCB Design Guidelines x
1.4.3.1. F-Tile Features and Capabilities 1.4.3.2. Optimizing the Passive Channel 1.4.3.3. COM Simulations 1.4.3.4. Simulating the Active Channel
1.4.5. R-Tile PCB Guidelines x
1.4.5.1. R-Tiles Features and Capabilities 1.4.5.2. R-Tile Design Layout Examples 1.4.5.3. Landing Pad Cut-out Optimization of AC Coupling Capacitor 1.4.5.4. R-tile HSSI Breakout Routing in BGA Area and MCIO connector Pin Area 1.4.5.5. AC Coupling Capacitor Placement Around MCIO Connector 1.4.5.6. PCIe Gen5 Add-in Card Edge Finger Breakout Design Guidelines
1. Signal Integrity (SI) in High-Speed PCB Designs

1.4.3.2. Optimizing the Passive Channel

You should optimize the whole channel from FPGA BGA pad to module IC pad. You only need to focus on optimizing the channel on the PCB, from FPGA BGA pad to optical connector footprint because the optical module is already optimized according to the vendor protocol specification. Refer to the General PCB Design Guidelines for general recommendations on how to optimize PCB channel. You can start board design with referencing to Intel FPGA development kits. Refer to All Development Kits.
Figure 21. Typical CEI-112G-VSR channel
  1. Use 3D EM tools for via structure optimization, including FPGA BGA breakout via and optical connector fan out via.
  2. Include connector 3D model for connector fan out via optimization, connector vendor typically can provide encrypted 3D model for connector and PCB joint simulation.
    Figure 22. Connectors
  3. Include crosstalk effects for all components in the simulation (FPGA BGA vias, traces, connector fan out vias)
  4. After you finish the optimization for each element of the channel, cascade them to build a passive channel (from ball to ball) to get channel performance, typically in S parameter format.
  5. Produce traditional channel performance plots like insertion loss, return loss, crosstalk and mode conversion from the channel S parameter to understand the channel performance.
  6. Further optimize it if you find any defects.
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