Agilex™ 7 Device Family High-Speed Serial Interface Signal Integrity Design Guidelines

Download PDF
ID 683864
Date 11/20/2024
Public
Document Table of Contents
Document Table of Contents x
1. Signal Integrity (SI) in High-Speed PCB Designs
1. Signal Integrity (SI) in High-Speed PCB Designs x
1.1. Supported Protocols 1.2. Channel Insertion Loss (IL) Budget Calculation 1.3. PCB Materials and Stackup Design Guidelines 1.4. PCB Design Guidelines 1.5. Document Revision History for the Agilex™ 7 Device Family High-Speed Serial Interface Signal Integrity Design Guidelines
1.3. PCB Materials and Stackup Design Guidelines x
1.3.1. Mitigating Insertion Loss with Dielectric Material 1.3.2. Power Layers 1.3.3. Reference Planes 1.3.4. Layer Assignment 1.3.5. Impedance 1.3.6. Via Drill Size 1.3.7. Fiber Weave 1.3.8. Reference Stackup
1.4. PCB Design Guidelines x
1.4.1. General PCB Design Guidelines 1.4.2. E-Tile PCB Design Guidelines 1.4.3. F-Tile PCB Design Guidelines 1.4.4. P-Tile PCB Design Guidelines 1.4.5. R-Tile PCB Guidelines
1.4.1. General PCB Design Guidelines x
1.4.1.1. PCB Traces 1.4.1.2. PCB Vias 1.4.1.3. Connector Breakout 1.4.1.4. AC Coupling Capacitor 1.4.1.5. Others
1.4.3. F-Tile PCB Design Guidelines x
1.4.3.1. F-Tile Features and Capabilities 1.4.3.2. Optimizing the Passive Channel 1.4.3.3. COM Simulations 1.4.3.4. Simulating the Active Channel
1.4.5. R-Tile PCB Guidelines x
1.4.5.1. R-Tiles Features and Capabilities 1.4.5.2. R-Tile Design Layout Examples 1.4.5.3. Landing Pad Cut-out Optimization of AC Coupling Capacitor 1.4.5.4. R-tile HSSI Breakout Routing in BGA Area and MCIO connector Pin Area 1.4.5.5. AC Coupling Capacitor Placement Around MCIO Connector 1.4.5.6. PCIe Gen5 Add-in Card Edge Finger Breakout Design Guidelines
1. Signal Integrity (SI) in High-Speed PCB Designs

1.5. Document Revision History for the Agilex™ 7 Device Family High-Speed Serial Interface Signal Integrity Design Guidelines

Document Version Changes
2024.11.20
  • Updated Impedance to clarify the limit for stripline impedance.
  • Updated Reference Stackup to clarify the Type-III PCIe.
  • Updated the following figure and topics to add more clarity:
    • Figure: Signal Integrity Flow in High-Speed PCB Designs
    • Mitigating Insertion Loss with Dielectric Material
    • PCB Traces
    • PCB Vias
  • Updated the following topics to the latest guidelines:
    • E-Tile PCB Design Guidelines
    • F-Tile PCB Design Guidelines
    • P-Tile PCB Design Guidelines
    • R-Tile PCB Design Guidelines
  • Updated the following figures in Landing Pad Cut-out Optimization of AC Coupling Capacitor:
    • Capacitor Pad Size and the Cut-out Optimization Results
    • TDR Simulation Result of 0201 Capacitor Cut-Out
2023.06.15 Updated product family name to " Agilex™ 7".
2022.09.26 Added miscellaneous changes
2021.03.18 Added F-tile and R-tile Design Guidelines.
2020.07.10 Initial release.
Level Two Title