Agilex™ 7 Device Family High-Speed Serial Interface Signal Integrity Design Guidelines

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ID 683864
Date 11/20/2024
Public
Document Table of Contents
Document Table of Contents x
1. Signal Integrity (SI) in High-Speed PCB Designs
1. Signal Integrity (SI) in High-Speed PCB Designs x
1.1. Supported Protocols 1.2. Channel Insertion Loss (IL) Budget Calculation 1.3. PCB Materials and Stackup Design Guidelines 1.4. PCB Design Guidelines 1.5. Document Revision History for the Agilex™ 7 Device Family High-Speed Serial Interface Signal Integrity Design Guidelines
1.3. PCB Materials and Stackup Design Guidelines x
1.3.1. Mitigating Insertion Loss with Dielectric Material 1.3.2. Power Layers 1.3.3. Reference Planes 1.3.4. Layer Assignment 1.3.5. Impedance 1.3.6. Via Drill Size 1.3.7. Fiber Weave 1.3.8. Reference Stackup
1.4. PCB Design Guidelines x
1.4.1. General PCB Design Guidelines 1.4.2. E-Tile PCB Design Guidelines 1.4.3. F-Tile PCB Design Guidelines 1.4.4. P-Tile PCB Design Guidelines 1.4.5. R-Tile PCB Guidelines
1.4.1. General PCB Design Guidelines x
1.4.1.1. PCB Traces 1.4.1.2. PCB Vias 1.4.1.3. Connector Breakout 1.4.1.4. AC Coupling Capacitor 1.4.1.5. Others
1.4.3. F-Tile PCB Design Guidelines x
1.4.3.1. F-Tile Features and Capabilities 1.4.3.2. Optimizing the Passive Channel 1.4.3.3. COM Simulations 1.4.3.4. Simulating the Active Channel
1.4.5. R-Tile PCB Guidelines x
1.4.5.1. R-Tiles Features and Capabilities 1.4.5.2. R-Tile Design Layout Examples 1.4.5.3. Landing Pad Cut-out Optimization of AC Coupling Capacitor 1.4.5.4. R-tile HSSI Breakout Routing in BGA Area and MCIO connector Pin Area 1.4.5.5. AC Coupling Capacitor Placement Around MCIO Connector 1.4.5.6. PCIe Gen5 Add-in Card Edge Finger Breakout Design Guidelines
1. Signal Integrity (SI) in High-Speed PCB Designs

1.4.3. F-Tile PCB Design Guidelines

  • Use a trace impedance of 90-100 Ω for differential signals. The nominal package impedance of the Agilex™ 7 FPGA device interface is 90 Ω.

  • Intra pair skew:±1 mil
  • Route lanes on shallow layers to reduce via length, with connectors placed on the PCB close to the FPGA to reduce the trace length.
  • Make via stubs as short as possible. Use back-drill, as necessary to shorten the via stubs. Stub lengths of less than 10 mils are recommended.
  • Use layer assignment to keep the coupling length of the closest TX and RX vias as short as possible.
  • Use additional ground reference vias for the package edge differential pairs in order to keep ground reference via symmetry for the two signal vias that comprise a differential pair.

For F-tile transceivers, the highest data rate and most challenging protocol is 400G Ethernet application (defined by CEI-112G-VSR/MR/LR or IEEE 802.3ck specification) with a data rate of up to 116G PAM4. This topic focuses on this application. For protocols which require FGT PAM4 usage, in order to ensure BER compliance, please contact Altera Customer Support and reference case 14023487435. For other applications with lower data rates, refer to the E-tile and P-tile design guidelines.

To design a 400G application interface on a CEI-112G compliant board, the typical design flow is:

  • Optimize the passive channel
  • COM simulation
  • Simulate the active channel

Section Content
F-Tile Features and Capabilities
Optimizing the Passive Channel
COM Simulations
Simulating the Active Channel

Level Two Title