Hybrid Memory Cube Controller IP Core User Guide - Intel Stratix 10 Beta Version

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ID 683854
Date 8/08/2016
Public
Document Table of Contents
Document Table of Contents x
1. About the Hybrid Memory Cube Controller IP Core 2. Getting Started with the HMC Controller IP Core 3. Functional Description 4. HMC Controller IP Core Signals 5. HMC Controller IP Core Register Map 6. HMC Controller IP Core Stratix 10 Design Example A. HMC Controller IP Core User Guide Archives B. Additional Information
1. About the Hybrid Memory Cube Controller IP Core x
1.1. HMC Controller IP Core Supported Features 1.2. HMC Controller IP Core Supported HMC Transaction Types 1.3. Device Family Support 1.4. IP Core Verification 1.5. Performance and Resource Utilization 1.6. Device Speed Grade Support 1.7. Release Information
1.4. IP Core Verification x
1.4.1. Simulation
2. Getting Started with the HMC Controller IP Core x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying IP Core Parameters and Options 2.3. HMC Controller IP Core Parameters 2.4. Files Generated for Intel FPGA IP Cores 2.5. Integrating Your IP Core in Your Design 2.6. Simulating Intel FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.3. HMC Controller IP Core Parameters x
2.3.1. RX Mapping and TX Mapping Parameters
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Constraints 2.5.2. Required External Blocks
2.5.2. Required External Blocks x
2.5.2.1. Adding the External PLL 2.5.2.2. Adding the External I2C Master Module
3. Functional Description x
3.1. High Level Block Diagram 3.2. Interfaces Overview 3.3. Clocking Structure 3.4. Initialization and Reset 3.5. M20K ECC Support 3.6. Flow Control 3.7. Error Detection and Management 3.8. Testing Features
3.2. Interfaces Overview x
3.2.1. Application Interfaces 3.2.2. HMC Interface 3.2.3. Interface to External I2C Master 3.2.4. Control and Status Register Interface 3.2.5. Status and Debug Interface 3.2.6. Transceiver Control Interfaces
3.2.6. Transceiver Control Interfaces x
3.2.6.1. External PLL Interface 3.2.6.2. Transceiver Reconfiguration Interface
4. HMC Controller IP Core Signals x
4.1. Application Interface Signals 4.2. HMC Interface Signals 4.3. Signals on the Interface to the I2C Master 4.4. Control and Status Register Interface Signals 4.5. Status and Debug Signals 4.6. Clock and Reset Signals 4.7. Transceiver Reconfiguration Signals 4.8. Signals on the Interface to the External PLL
4.1. Application Interface Signals x
4.1.1. Application Request Interface 4.1.2. Application Response Interface 4.1.3. HMC Controller IP Core Data Path Example
5. HMC Controller IP Core Register Map x
5.1. CONTROL Register 5.2. XCVR_STATUS Register 5.3. LANE_STATUS Register 5.4. LINK_STATUS Register 5.5. ERROR_RESPONSE Register 5.6. LIMIT_OUTSTANDING_PACKETS Register 5.7. Interrupt Related Registers 5.8. Error and Retry Statistics Registers
B. Additional Information x
B.1. HMC Controller IP Core User Guide Revision History
1. About the Hybrid Memory Cube Controller IP Core
2. Getting Started with the HMC Controller IP Core
3. Functional Description
4. HMC Controller IP Core Signals
5. HMC Controller IP Core Register Map
6. HMC Controller IP Core Stratix 10 Design Example
A. HMC Controller IP Core User Guide Archives
B. Additional Information

4.3. Signals on the Interface to the I2C Master

Your design must include an I2C master module that drives the HMC device I2C interface for link initialization. This interface connects to the I2C module.

The I2C module and the IP core together must implement the following four-way handshake with the two interface signals:

  1. Resetting the IP core deasserts the i2c_load_registers signal. Resetting the I2C master module should deassert the i2c_registers_loaded signal.
  2. When the IP core and the HMC are ready, the IP core asserts i2c_load_registers. In simulation, the IP core assumes the HMC simulation model is ready instantaneously, and in hardware, the IP core waits the required tINIT duration of 20 ms.
  3. After the I2C master module detects the assertion of i2c_load_registers, it writes to the HMC device registers to set them up for link initialization (concluding with Init Continue) and then asserts the i2c_registers_loaded signal.
  4. The HMC Controller IP core deasserts i2c_load_registers.
  5. The I2C master module deasserts i2c_registers_loaded.
Table 14.  Signals on the Interface to the External I2C Master ModuleThe IP core i2c_load_registers signal behavior conforms to the four-way handshaking protocol. For correct HMC Controller IP core functionality, you must design the I2C master module in your design to implement i2c_registers_loaded signal behavior that conforms to this four-way handshaking protocol.

Signal Name

Direction

Description

i2c_load_registers

Output

Indicates the HMC Controller IP core is ready for the external I2C master module to load the HMC device configuration registers, as part of the link initialization sequence.

You must connect this signal to the I2C master module input port that accepts requests to load the configuration registers of the HMC device.

i2c_registers_loaded

Input

Indicates the external HMC device registers are configured.

You must connect this signal to the output port of the I2C master that indicates successful completion of the configuration register load sequence.

If multiple HMC Controller IP cores are connected to different links of the same HMC device, the external I2C master must wait until all of the HMC Controller IP cores have asserted their i2c_load_registers signal, before writing to the HMC device configuration registers. After the external I2C master completes writing all of the HMC configuration registers, it must assert the i2c_registers_loaded signals for all of the HMC Controller IP cores simultaneously.

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