Hybrid Memory Cube Controller IP Core User Guide - Intel Stratix 10 Beta Version

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ID 683854
Date 8/08/2016
Public
Document Table of Contents
Document Table of Contents x
1. About the Hybrid Memory Cube Controller IP Core 2. Getting Started with the HMC Controller IP Core 3. Functional Description 4. HMC Controller IP Core Signals 5. HMC Controller IP Core Register Map 6. HMC Controller IP Core Stratix 10 Design Example A. HMC Controller IP Core User Guide Archives B. Additional Information
1. About the Hybrid Memory Cube Controller IP Core x
1.1. HMC Controller IP Core Supported Features 1.2. HMC Controller IP Core Supported HMC Transaction Types 1.3. Device Family Support 1.4. IP Core Verification 1.5. Performance and Resource Utilization 1.6. Device Speed Grade Support 1.7. Release Information
1.4. IP Core Verification x
1.4.1. Simulation
2. Getting Started with the HMC Controller IP Core x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying IP Core Parameters and Options 2.3. HMC Controller IP Core Parameters 2.4. Files Generated for Intel FPGA IP Cores 2.5. Integrating Your IP Core in Your Design 2.6. Simulating Intel FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.3. HMC Controller IP Core Parameters x
2.3.1. RX Mapping and TX Mapping Parameters Example: Non-Default RX Mapping Parameter Value Example: Non-Default TX Mapping Parameter Value
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Constraints 2.5.2. Required External Blocks
2.5.2. Required External Blocks x
2.5.2.1. Adding the External PLL 2.5.2.2. Adding the External I2C Master Module
3. Functional Description x
3.1. High Level Block Diagram 3.2. Interfaces Overview 3.3. Clocking Structure 3.4. Initialization and Reset 3.5. M20K ECC Support 3.6. Flow Control 3.7. Error Detection and Management 3.8. Testing Features
3.2. Interfaces Overview x
3.2.1. Application Interfaces 3.2.2. HMC Interface 3.2.3. Interface to External I2C Master 3.2.4. Control and Status Register Interface 3.2.5. Status and Debug Interface 3.2.6. Transceiver Control Interfaces
3.2.6. Transceiver Control Interfaces x
3.2.6.1. External PLL Interface 3.2.6.2. Transceiver Reconfiguration Interface
4. HMC Controller IP Core Signals x
4.1. Application Interface Signals 4.2. HMC Interface Signals 4.3. Signals on the Interface to the I2C Master 4.4. Control and Status Register Interface Signals 4.5. Status and Debug Signals 4.6. Clock and Reset Signals 4.7. Transceiver Reconfiguration Signals 4.8. Signals on the Interface to the External PLL
4.1. Application Interface Signals x
4.1.1. Application Request Interface 4.1.2. Application Response Interface 4.1.3. HMC Controller IP Core Data Path Example
5. HMC Controller IP Core Register Map x
5.1. CONTROL Register 5.2. XCVR_STATUS Register 5.3. LANE_STATUS Register 5.4. LINK_STATUS Register 5.5. ERROR_RESPONSE Register 5.6. LIMIT_OUTSTANDING_PACKETS Register 5.7. Interrupt Related Registers 5.8. Error and Retry Statistics Registers
B. Additional Information x
B.1. HMC Controller IP Core User Guide Revision History
1. About the Hybrid Memory Cube Controller IP Core
2. Getting Started with the HMC Controller IP Core
3. Functional Description
4. HMC Controller IP Core Signals
5. HMC Controller IP Core Register Map
6. HMC Controller IP Core Stratix 10 Design Example
A. HMC Controller IP Core User Guide Archives
B. Additional Information

2.3.1. RX Mapping and TX Mapping Parameters

The HMC Controller IP core provides the RX mapping and TX mapping parameters for flexibility in board design.

The default values of these parameters specify the correct IP core behavior when the HMC device LxTX[<i>] output signal connects to the HMC Controller IP core hmc_lxrx[<i>] input port, and the LxRX[<i>] input signal connects to the HMC Controller IP core hmc_lxtx[<i>] output port, for each <i>.

However, if your design constraints prevent you from connecting these signals as expected, you can instead modify one or both HMC Controller IP core mapping parameters to accommodate the non-standard connection.

Note: The Quartus® Prime Fitter prevents you from mapping the HMC Controller IP core lanes to device transceiver channels out of order. Therefore, these two parameters only compensate for out-of-order connections on the board between the device transceiver pins and the HMC device ports.
Figure 4. Default RX and TX Mapping Parameter Values


If the HMC device LxTX[<i>] output signal connects to the HMC Controller IP core hmc_lxrx[<k>] input port, you must set the value in bits [(4<i>+3):(4<i>)] (nibble <i>) of the RX mapping parameter to 4'h<k>. Therefore, the default value of the RX mapping parameter is 0xFEDCBA9876543210, indicating that LxTX[F] connects to hmc_lxrx[F], LxTX[E] connects to hmc_lxrx[E], and so on.

If the HMC device LxRX[<i>] input signal connects to the HMC Controller IP core hmc_lxtx[<k>] input port, you must set the value in bits [(4<i>+3):(4<i>)] (nibble <i>) of the TX mapping parameter to 4'h<k>. Therefore, the default value of the TX mapping parameter is 0xFEDCBA9876543210, indicating that LxRX[F] connects to hmc_lxtx[F], LxRX[E] connects to hmc_lxtx[E], and so on.

Example: Non-Default RX Mapping Parameter Value

Table 8.  Non-Default RX Connections
HMC Device Output Signal IP Core Input Signal
LxTX[2] hmc_lxrx[0]
LxTX[1] hmc_lxrx[2]
LxTX[0] hmc_lxrx[1]
Figure 5. Non-Default RX Mapping Parameter Value ExampleIf you connect the IP core hmc_lxrx[2:0] input signals according to the table, and connect all other IP core hmc_lxrx[<i>] input ports to the corresponding HMC device LxTX[<i>] output ports, you would set the value of the RX mapping parameter to 0xFEDCBA9876543021 to compensate for the non-standard connection.
Note: The RX mapping parameter specifies the HMC device lane by position and the IP core lane by value. The figure illustrates a mapping parameter value of 0xFED.......43021 and not a value of 0xFED....43102.


Example: Non-Default TX Mapping Parameter Value

Table 9.  Non-Default TX Connections
HMC Device Input Signal IP Core Output Signal
LxRX[2] hmc_lxtx[0]
LxRX[1] hmc_lxtx[2]
LxRX[0] hmc_lxtx[1]
Figure 6. Non-Default TX Mapping Parameter Value ExampleIf you connect the HMC Controller IP core hmc_lxtx[2:0] output signals according to the table, and connect all other IP core hmc_lxtx[<i>] output ports to the corresponding HMC device LxRX[<i>] input ports, you would set the value of the TX mapping parameter to 0xFEDCBA9876543021 to compensate for the non-standard connection.
Note: The TX mapping parameter specifies the HMC device lane by position and the IP core lane by value. The figure illustrates a mapping parameter value of 0xFED.......43021 and not a value of 0xFED....43102.


Use caution in modifying these parameters. In loopback configurations, you must ensure the RX mapping and TX mapping parameters specify reversed mappings. Otherwise, the IP core downstream of the RX lane swapper appears to receive data on the wrong lanes.

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