Hybrid Memory Cube Controller IP Core User Guide - Intel Stratix 10 Beta Version

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ID 683854
Date 8/08/2016
Public
Document Table of Contents
Document Table of Contents x
1. About the Hybrid Memory Cube Controller IP Core 2. Getting Started with the HMC Controller IP Core 3. Functional Description 4. HMC Controller IP Core Signals 5. HMC Controller IP Core Register Map 6. HMC Controller IP Core Stratix 10 Design Example A. HMC Controller IP Core User Guide Archives B. Additional Information
1. About the Hybrid Memory Cube Controller IP Core x
1.1. HMC Controller IP Core Supported Features 1.2. HMC Controller IP Core Supported HMC Transaction Types 1.3. Device Family Support 1.4. IP Core Verification 1.5. Performance and Resource Utilization 1.6. Device Speed Grade Support 1.7. Release Information
1.4. IP Core Verification x
1.4.1. Simulation
2. Getting Started with the HMC Controller IP Core x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying IP Core Parameters and Options 2.3. HMC Controller IP Core Parameters 2.4. Files Generated for Intel FPGA IP Cores 2.5. Integrating Your IP Core in Your Design 2.6. Simulating Intel FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.3. HMC Controller IP Core Parameters x
2.3.1. RX Mapping and TX Mapping Parameters
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Constraints 2.5.2. Required External Blocks
2.5.2. Required External Blocks x
2.5.2.1. Adding the External PLL 2.5.2.2. Adding the External I2C Master Module
3. Functional Description x
3.1. High Level Block Diagram 3.2. Interfaces Overview 3.3. Clocking Structure 3.4. Initialization and Reset 3.5. M20K ECC Support 3.6. Flow Control 3.7. Error Detection and Management 3.8. Testing Features
3.2. Interfaces Overview x
3.2.1. Application Interfaces 3.2.2. HMC Interface 3.2.3. Interface to External I2C Master 3.2.4. Control and Status Register Interface 3.2.5. Status and Debug Interface 3.2.6. Transceiver Control Interfaces
3.2.6. Transceiver Control Interfaces x
3.2.6.1. External PLL Interface 3.2.6.2. Transceiver Reconfiguration Interface
4. HMC Controller IP Core Signals x
4.1. Application Interface Signals 4.2. HMC Interface Signals 4.3. Signals on the Interface to the I2C Master 4.4. Control and Status Register Interface Signals 4.5. Status and Debug Signals 4.6. Clock and Reset Signals 4.7. Transceiver Reconfiguration Signals 4.8. Signals on the Interface to the External PLL
4.1. Application Interface Signals x
4.1.1. Application Request Interface 4.1.2. Application Response Interface 4.1.3. HMC Controller IP Core Data Path Example
5. HMC Controller IP Core Register Map x
5.1. CONTROL Register 5.2. XCVR_STATUS Register 5.3. LANE_STATUS Register 5.4. LINK_STATUS Register 5.5. ERROR_RESPONSE Register 5.6. LIMIT_OUTSTANDING_PACKETS Register 5.7. Interrupt Related Registers 5.8. Error and Retry Statistics Registers
B. Additional Information x
B.1. HMC Controller IP Core User Guide Revision History
1. About the Hybrid Memory Cube Controller IP Core
2. Getting Started with the HMC Controller IP Core
3. Functional Description
4. HMC Controller IP Core Signals
5. HMC Controller IP Core Register Map
6. HMC Controller IP Core Stratix 10 Design Example
A. HMC Controller IP Core User Guide Archives
B. Additional Information

2.3. HMC Controller IP Core Parameters

The HMC Controller parameter editor provides the parameters you can set to configure the HMC Controller IP core and simulation testbenches.

The HMC Controller parameter editor includes an Example Design tab. For information about that tab, refer to the Hybrid Memory Controller Design Example User Guide.

Table 7.  HMC Controller IP Core ParametersParameters for customizing the HMC Controller IP core in the IP tab of the HMC Controller parameter editor.

Parameter

Type

Range

Default Setting

Parameter Description

Lanes

Integer

  • 16

16

Selects full-width (16 lanes) functionality.

IP cores that target a Stratix 10 device do not support half-width functionality.

Data rate

String

  • 10 Gbps
  • 12.5 Gbps
  • 15 Gbps

10 Gbps

Selects the data rate on each lane.

CDR reference clock

String

  • 125 MHz
  • 156.25 MHz
  • 166.67 MHz (available only for Data rate 10 Gbps or 15 Gbps)

125 MHz

Selects the frequency of the input reference clock for the RX CDR PLL. You must drive the rx_cdr_refclk0 input signal at the frequency you specify for this parameter.

In addition, your design must derive this clock, the external transceiver TX PLL reference clock, and the REFCLKP and REFCLKN input signals of the external HMC device from the same clock source.

Ports Integer
  • 1
  • 2
  • 3
  • 4
1 Number of ports (data path interfaces).

Increasing the number of ports increases utilization of the Hybrid Memory Cube, increasing efficiency. However, it may increase request-to-response latency on each individual port, as the IP core arbitrates among the incoming requests.

If you specify more than one port, each port is assigned a range of tags.

  • If you specify 2 ports, port 0 must use tags in the range 0 to 255, and port 1 must use tags in the range 256 to 511.
  • If you specify 3 ports, port 0 must use tags in the range 0 to 175, port 1 must use tags in the range 176 to 351, and port 2 must use tags in the range 352 to 511.
  • If you specify 4 ports, port 0 must use tags in the range 0 to 127, port 1 must use tags in the range 128 to 255, port 2 must use tags in the range 256 to 383, and port 3 must use tags in the range 384 to 511.
Enable response re-ordering Boolean
  • True
  • False
False Specifies whether the IP core ensures that responses appear on each data response interface in the order the original requests arrived on the corresponding request interface.

If you turn on this feature, the IP core manages tags internally. In that case tags are not available on the data interfaces.

Turning on this feature can increase round-trip latency.

RX mapping

64-bit value

0xFEDCBA9876543210

Selects the RX lane mapping.

Use caution in modifying this parameter. Refer to RX Mapping and TX Mapping Parameters.

TX mapping

64-bit value

0xFEDCBA9876543210

Selects the TX lane mapping.

Use caution in modifying this parameter. Refer to RX Mapping and TX Mapping Parameters.

Enable M20K ECC support

Boolean

  • True
  • False
False

Specifies whether the IP core supports the ECC feature in the device M20K memory blocks that are configured as part of the IP core.

You can turn on this parameter to enhance data reliability by enabling single-error correction, double-adjacent-error correction, and triple-adjacent-error correction ECC functionality in the M20K memory blocks configured in your IP core. Turn off this parameter to decrease latency and resource utilization.


Section Content
RX Mapping and TX Mapping Parameters

Level Two Title