Hybrid Memory Cube Controller IP Core User Guide - Intel Stratix 10 Beta Version

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ID 683854
Date 8/08/2016
Public
Document Table of Contents
Document Table of Contents x
1. About the Hybrid Memory Cube Controller IP Core 2. Getting Started with the HMC Controller IP Core 3. Functional Description 4. HMC Controller IP Core Signals 5. HMC Controller IP Core Register Map 6. HMC Controller IP Core Stratix 10 Design Example A. HMC Controller IP Core User Guide Archives B. Additional Information
1. About the Hybrid Memory Cube Controller IP Core x
1.1. HMC Controller IP Core Supported Features 1.2. HMC Controller IP Core Supported HMC Transaction Types 1.3. Device Family Support 1.4. IP Core Verification 1.5. Performance and Resource Utilization 1.6. Device Speed Grade Support 1.7. Release Information
1.4. IP Core Verification x
1.4.1. Simulation
2. Getting Started with the HMC Controller IP Core x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying IP Core Parameters and Options 2.3. HMC Controller IP Core Parameters 2.4. Files Generated for Intel FPGA IP Cores 2.5. Integrating Your IP Core in Your Design 2.6. Simulating Intel FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.3. HMC Controller IP Core Parameters x
2.3.1. RX Mapping and TX Mapping Parameters
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Constraints 2.5.2. Required External Blocks
2.5.2. Required External Blocks x
2.5.2.1. Adding the External PLL 2.5.2.2. Adding the External I2C Master Module
3. Functional Description x
3.1. High Level Block Diagram 3.2. Interfaces Overview 3.3. Clocking Structure 3.4. Initialization and Reset 3.5. M20K ECC Support 3.6. Flow Control 3.7. Error Detection and Management 3.8. Testing Features
3.2. Interfaces Overview x
3.2.1. Application Interfaces 3.2.2. HMC Interface 3.2.3. Interface to External I2C Master 3.2.4. Control and Status Register Interface 3.2.5. Status and Debug Interface 3.2.6. Transceiver Control Interfaces
3.2.6. Transceiver Control Interfaces x
3.2.6.1. External PLL Interface 3.2.6.2. Transceiver Reconfiguration Interface
4. HMC Controller IP Core Signals x
4.1. Application Interface Signals 4.2. HMC Interface Signals 4.3. Signals on the Interface to the I2C Master 4.4. Control and Status Register Interface Signals 4.5. Status and Debug Signals 4.6. Clock and Reset Signals 4.7. Transceiver Reconfiguration Signals 4.8. Signals on the Interface to the External PLL
4.1. Application Interface Signals x
4.1.1. Application Request Interface 4.1.2. Application Response Interface 4.1.3. HMC Controller IP Core Data Path Example
5. HMC Controller IP Core Register Map x
5.1. CONTROL Register 5.2. XCVR_STATUS Register 5.3. LANE_STATUS Register 5.4. LINK_STATUS Register 5.5. ERROR_RESPONSE Register 5.6. LIMIT_OUTSTANDING_PACKETS Register 5.7. Interrupt Related Registers 5.8. Error and Retry Statistics Registers
B. Additional Information x
B.1. HMC Controller IP Core User Guide Revision History
1. About the Hybrid Memory Cube Controller IP Core
2. Getting Started with the HMC Controller IP Core
3. Functional Description
4. HMC Controller IP Core Signals
5. HMC Controller IP Core Register Map
6. HMC Controller IP Core Stratix 10 Design Example
A. HMC Controller IP Core User Guide Archives
B. Additional Information

4.1.2. Application Response Interface

The data path response interface, or application response interface, provides a 512-bit data bus and dedicated signals for the IP core to provide HMC response information to the application. The interface supports Read responses with payload sizes up to 128 bytes. The maximum payload size limits the interface to data bursts of 2 or fewer core_clk clock cycles. Read responses with a payload size that is not a multiple of the bus size carry the end of the payload in the lower order bits of the data bus in the final clock cycle.

If you turn off Response re-ordering , the HMC Controller returns the 9-bit tag from the original request with every response it sends on the data path response interface. The application must use the tag to match each response with the corresponding request.

You cannot back-pressure the IP core data path response interface. To ensure the application can process every response it receives, the application must only send requests for which it has the resources to process or buffer the response.

Figure 18. HMC Controller IP Core With Single Port to RX ApplicationThe HMC Controller IP core acts as a source and the client acts as a sink in the receive direction.
Figure 19. HMC Controller IP Core With Multiple Ports to RX ApplicationThe HMC Controller IP core acts as a source and the client acts as a sink in the receive direction. N is the number of ports you specify with the Ports parameter.
Table 12.  Signals of Each Data Path Response InterfaceAll interface signals are clocked by the core_clk clock. If the IP core has multiple ports, the port number is part of the signal name, as shown. If the IP core has a single port, the port number is not included in the signal name, for backward compatibility with previous releases of the IP core. If the IP core has two ports, it has two sets of signals, one with n=0 and one with n=1. If the IP core has three ports, it has three sets of signals, with n=0, 1, and 2. If the IP core has four ports, it has four sets of signals, with n=0, 1, 2, and 3.

Signal Name

Direction

Description

dp<n>_rsp_valid

Output

Indicates that all of the dp<n>_rsp_tag, dp<n>_rsp_cmd, dp<n>_rsp_error, dp<n>_rsp_sop, dp<n>_rsp_eop, and dp<n>_rsp_errstat signals are valid, and in a read response with payload, dp<n>_rsp_data and dp<n>_rsp_size are valid.

The application must accept all valid transactions. You cannot back-pressure the HMC Controller IP core data path response interface.

The IP core maintains this signal asserted for the duration of a multi-cycle read data transfer.

dp<n>_rsp_tag[8:0]

Output

The tag associated with the original request to which this is a response.

After you process this response, the tag is available for re-use.

The IP core maintains the value of this signal for the duration of a multi-cycle read data transfer.

This signal is not available if you turn on Response re-ordering. In that case the IP core manages tags internally.

dp<n>_rsp_cmd[5:0]

Output

Indicates the packet command associated with this response. Refer to Table 25 in the HMC Specification v1.1 for the command encodings. This signal holds only non-error response codes; the IP core routes error responses to the registers.

The IP core maintains the value of this signal for the duration of a multi-cycle read data transfer.

dp<n>_rsp_size[2:0]

Output

Indicates the size of the payload associated with this response. If the current response is a Read response, indicates the size of the payload in dp<n>_rsp_data.

During a response with an associated payload, the IP core sets this signal to one of the following valid values:

  • 3'b000 indicates a 16-byte payload.
  • 3'b001 indicates a 32-byte payload.
  • 3'b010 indicates a 48-byte payload.
  • 3'b011 indicates a 64-byte payload.
  • 3'b100 indicates a 80-byte payload.
  • 3'b101 indicates a 96-byte payload.
  • 3'b110 indicates a 112-byte payload.
  • 3'b111 indicates a 128-byte payload.

During a response with no associated payload, the value of this signal is undefined. Responses with no associated payload are the responses for which dp<n>_rsp_cmd[0] has the value of 1.

The IP core maintains the value of this signal for the duration of a multi-cycle read data transfer.

dp<n>_rsp_data[511:0]

Output

Read response data.

During a response with no associated payload, the value of this signal is undefined. Responses with no associated payload are the responses for which dp<n>_rsp_cmd[0] has the value of 1.

If the size of the payload is not an integer multiple of the data bus width, then in the final data transfer cycle, the IP core transfers the remaining read payload in the least significant bytes of dp<n>_rsp_data or dp_rsp_data. For example, the IP core:

  • Transfers a 16-byte payload in dp_rsp_data[127:0].
  • Transfers a 32-byte payload in dp_rsp_data[255:0].
  • Transfers the final (most significant) 48 bytes of a 112-byte payload in dp_rsp_data[383:0] in the second data transfer clock cycle.
dp<n>_rsp_error

Output

Indicates that the corresponding request completed with an error and will not be retried automatically. The HMC Controller IP core asserts this signal if it received a Read or Write response packet from the external HMC device with a non-zero ERRSTAT or DINV field.

The IP core maintains the value of this signal for the duration of a multi-cycle read data transfer.

dp<n>_rsp_sop Output Start of packet. The IP core asserts this signal in the first cycle of all response transactions.
dp<n>_rsp_eop Output End of packet. The IP core asserts this signal in the final cycle of all response transactions.
dp<n>_rsp_errstat[6:0] Output Error status. The IP core passes this value directly from the external HMC device ERRSTAT field.
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