Hybrid Memory Cube Controller IP Core User Guide - Intel Stratix 10 Beta Version

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ID 683854
Date 8/08/2016
Public
Document Table of Contents
Document Table of Contents x
1. About the Hybrid Memory Cube Controller IP Core 2. Getting Started with the HMC Controller IP Core 3. Functional Description 4. HMC Controller IP Core Signals 5. HMC Controller IP Core Register Map 6. HMC Controller IP Core Stratix 10 Design Example A. HMC Controller IP Core User Guide Archives B. Additional Information
1. About the Hybrid Memory Cube Controller IP Core x
1.1. HMC Controller IP Core Supported Features 1.2. HMC Controller IP Core Supported HMC Transaction Types 1.3. Device Family Support 1.4. IP Core Verification 1.5. Performance and Resource Utilization 1.6. Device Speed Grade Support 1.7. Release Information
1.4. IP Core Verification x
1.4.1. Simulation
2. Getting Started with the HMC Controller IP Core x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying IP Core Parameters and Options 2.3. HMC Controller IP Core Parameters 2.4. Files Generated for Intel FPGA IP Cores 2.5. Integrating Your IP Core in Your Design 2.6. Simulating Intel FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.3. HMC Controller IP Core Parameters x
2.3.1. RX Mapping and TX Mapping Parameters
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Constraints 2.5.2. Required External Blocks
2.5.2. Required External Blocks x
2.5.2.1. Adding the External PLL 2.5.2.2. Adding the External I2C Master Module
3. Functional Description x
3.1. High Level Block Diagram 3.2. Interfaces Overview 3.3. Clocking Structure 3.4. Initialization and Reset 3.5. M20K ECC Support 3.6. Flow Control 3.7. Error Detection and Management 3.8. Testing Features
3.2. Interfaces Overview x
3.2.1. Application Interfaces 3.2.2. HMC Interface 3.2.3. Interface to External I2C Master 3.2.4. Control and Status Register Interface 3.2.5. Status and Debug Interface 3.2.6. Transceiver Control Interfaces
3.2.6. Transceiver Control Interfaces x
3.2.6.1. External PLL Interface 3.2.6.2. Transceiver Reconfiguration Interface
4. HMC Controller IP Core Signals x
4.1. Application Interface Signals 4.2. HMC Interface Signals 4.3. Signals on the Interface to the I2C Master 4.4. Control and Status Register Interface Signals 4.5. Status and Debug Signals 4.6. Clock and Reset Signals 4.7. Transceiver Reconfiguration Signals 4.8. Signals on the Interface to the External PLL
4.1. Application Interface Signals x
4.1.1. Application Request Interface 4.1.2. Application Response Interface 4.1.3. HMC Controller IP Core Data Path Example
5. HMC Controller IP Core Register Map x
5.1. CONTROL Register 5.2. XCVR_STATUS Register 5.3. LANE_STATUS Register 5.4. LINK_STATUS Register 5.5. ERROR_RESPONSE Register 5.6. LIMIT_OUTSTANDING_PACKETS Register 5.7. Interrupt Related Registers 5.8. Error and Retry Statistics Registers
B. Additional Information x
B.1. HMC Controller IP Core User Guide Revision History
1. About the Hybrid Memory Cube Controller IP Core
2. Getting Started with the HMC Controller IP Core
3. Functional Description
4. HMC Controller IP Core Signals
5. HMC Controller IP Core Register Map
6. HMC Controller IP Core Stratix 10 Design Example
A. HMC Controller IP Core User Guide Archives
B. Additional Information

3.7. Error Detection and Management

The HMC specification defines error detection and recovery processes. The HMC Controller IP core complies with these requirements, and implements the following additional features to support error management:

  • Error Response queues to support software handling without dropping Error Responses that arrive in quick succession
  • Statistics registers that count the number of packets in various error categories
Table 10.  HMC Response Packet Field CheckingThe HMC Controller checks these HMC packet fields for error indications, and handles errors by entering Error Abort mode to force the HMC device to retransmit the packet. In this mode, the IP core completes transmission of any partially transmitted packet and then submits IRTRY packets, per the HMC specification. The IP core also sets the indicated bit in the INTERRUPT_STATUS register and increments the Local Count field of the LOCAL_ERROR_COUNT register.
Received Packet Field Error Indication INTERRUPT_STATUS Register Bit
LNG and DLN The two fields have different values, or an invalid value LNG/DLN Error
CRC Incorrect CRC CRC Error
SEQ Unexpected value SEQ Error

The HMC Controller IP core also checks the ERRSTAT field value and treats the response according to the following rules:

  • If ERRSTAT has the value of zero, this field indicates no errors or conditions. The IP core processes the response packet as usual.
  • If ERRSTAT has a non-zero value in a Read response, Write response, or MODE response packet, the IP core processes the response as usual, but asserts the dp_rsp_error signal on the RX data path interface when passing the response to the application.
  • If ERRSTAT has a non-zero value in an Error response packet, the IP core does not forward the Error response packet to the RX data path interface. Instead, the IP core diverts the packet's ERRSTAT and cube ID values to the internal Error Response FIFO. The first element of the internal Error Response FIFO is always readable in the ERROR_RESPONSE register. You can process these packets in software.
The HMC Controller IP core transmits 32 IRTRY packets in every retry sequence.
Note: The IP core expects to receive at least 20 IRTRY packets from the HMC device.
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