Hybrid Memory Cube Controller IP Core User Guide - Intel Stratix 10 Beta Version

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ID 683854
Date 8/08/2016
Public
Document Table of Contents
Document Table of Contents x
1. About the Hybrid Memory Cube Controller IP Core 2. Getting Started with the HMC Controller IP Core 3. Functional Description 4. HMC Controller IP Core Signals 5. HMC Controller IP Core Register Map 6. HMC Controller IP Core Stratix 10 Design Example A. HMC Controller IP Core User Guide Archives B. Additional Information
1. About the Hybrid Memory Cube Controller IP Core x
1.1. HMC Controller IP Core Supported Features 1.2. HMC Controller IP Core Supported HMC Transaction Types 1.3. Device Family Support 1.4. IP Core Verification 1.5. Performance and Resource Utilization 1.6. Device Speed Grade Support 1.7. Release Information
1.4. IP Core Verification x
1.4.1. Simulation
2. Getting Started with the HMC Controller IP Core x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying IP Core Parameters and Options 2.3. HMC Controller IP Core Parameters 2.4. Files Generated for Intel FPGA IP Cores 2.5. Integrating Your IP Core in Your Design 2.6. Simulating Intel FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.3. HMC Controller IP Core Parameters x
2.3.1. RX Mapping and TX Mapping Parameters
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Constraints 2.5.2. Required External Blocks
2.5.2. Required External Blocks x
2.5.2.1. Adding the External PLL 2.5.2.2. Adding the External I2C Master Module
3. Functional Description x
3.1. High Level Block Diagram 3.2. Interfaces Overview 3.3. Clocking Structure 3.4. Initialization and Reset 3.5. M20K ECC Support 3.6. Flow Control 3.7. Error Detection and Management 3.8. Testing Features
3.2. Interfaces Overview x
3.2.1. Application Interfaces 3.2.2. HMC Interface 3.2.3. Interface to External I2C Master 3.2.4. Control and Status Register Interface 3.2.5. Status and Debug Interface 3.2.6. Transceiver Control Interfaces
3.2.6. Transceiver Control Interfaces x
3.2.6.1. External PLL Interface 3.2.6.2. Transceiver Reconfiguration Interface
4. HMC Controller IP Core Signals x
4.1. Application Interface Signals 4.2. HMC Interface Signals 4.3. Signals on the Interface to the I2C Master 4.4. Control and Status Register Interface Signals 4.5. Status and Debug Signals 4.6. Clock and Reset Signals 4.7. Transceiver Reconfiguration Signals 4.8. Signals on the Interface to the External PLL
4.1. Application Interface Signals x
4.1.1. Application Request Interface 4.1.2. Application Response Interface 4.1.3. HMC Controller IP Core Data Path Example
5. HMC Controller IP Core Register Map x
5.1. CONTROL Register 5.2. XCVR_STATUS Register 5.3. LANE_STATUS Register 5.4. LINK_STATUS Register 5.5. ERROR_RESPONSE Register 5.6. LIMIT_OUTSTANDING_PACKETS Register 5.7. Interrupt Related Registers 5.8. Error and Retry Statistics Registers
B. Additional Information x
B.1. HMC Controller IP Core User Guide Revision History
1. About the Hybrid Memory Cube Controller IP Core
2. Getting Started with the HMC Controller IP Core
3. Functional Description
4. HMC Controller IP Core Signals
5. HMC Controller IP Core Register Map
6. HMC Controller IP Core Stratix 10 Design Example
A. HMC Controller IP Core User Guide Archives
B. Additional Information

B.1. HMC Controller IP Core User Guide Revision History

Document Version Quartus® Prime Version Changes
2018.07.10 Quartus® Prime Pro – Stratix 10 Edition Beta Renamed UG-01152 2016.08.08 to UG-20191 2016.08.08 and updated title.
Table 35.  Document Revision History Summarizes the new features and changes in the user guide for the HMC Controller IP core.

Date

ACDS Version

Changes

2016.08.08 Quartus® Prime Pro – Stratix 10 Edition Beta Updated for the Quartus® Prime Pro – Stratix 10 Edition Beta software release:
  • Added support for Stratix 10 devices.
  • Removed mention of Arria 10 variations of the IP core. This release supports only Stratix 10 devices.
  • Removed mention of half-width variations. Half-width variations are not supported in the Stratix 10 device family.
  • Noted some differences in supported simulators and the design example in this release. Refer to HMC Controller IP Core Stratix 10 Design Example.
  • Changed register names. Refer to HMC Controller IP Core Register Map.
  • Clarified that the Lanes and Enable ADME and Optional Reconfiguration Logic IP core parameters, although still visible in the IP core parameter editor, are not supported in this release. Refer to HMC Controller IP Core Parameters.
  • Clarified that the transceiver reconfiguration interface is not functional in this release. However, you must drive the reconfig_clk input at an appropriate clock frequency. Refer to Transceiver Reconfiguration Interface, Transceiver Reconfiguration Signals, and High Level Block Diagram.
  • Clarified that the rst_n and reconfig_reset input signals are asynchronous and must be asserted long enough for the IP core to capture the reset request. Refer to Clock and Reset Signals.
  • Updated the descriptions of the M20K ECC functionality from triple-adjacent-error detect (for Arria 10 devices) to triple-adjacent-error correct (for Stratix 10 devices). Refer to HMC Controller IP Core Parameters and M20K ECC Support.
  • Clarified that each HMC Controller IP core connects to a single HMC device link. To connect to multiple links of your HMC device, you must instantiate multiple instances of the HMC Controller IP core. Refer to HMC Controller IP Core Supported Features.
  • Removed erroneous indication that certain payload sizes are available only in half-width variations. Refer to Application Response Interface.
  • Changed title of "Clocking and Reset Structure" section to "Clocking Structure". This section does not contain reset information. Refer to Clocking Structure.
  • Fixed assorted typos and minor errors.
2016.05.02 16.0
  • Updated for Quartus Prime software v16.0 release.
  • Added support for multiple (2, 3, or 4) data interfaces in full-width variations.
  • Added new Response re-ordering parameter for full-width variations, to specify that the IP core should return responses on each data response interface in the order it received the original requests on the corresponding data request interface. When you turn on this new option, the IP core implements tag management internally, and the tags are not visible on the data interfaces. Refer to HMC Controller IP Core Supported Features and HMC Controller IP Core Parameters.
  • Expanded list of supported transactions by adding non-power of two payload sizes for READ, WRITE, and Posted WRITE transactions in full-width variations. Full-width variations now support all transaction types that half-width variations support. Refer to HMC Controller IP Core Supported HMC Transaction Types.
  • Changed name of Enable Altera Debug Master Endpoint (ADME) parameter to Enable ADME and Optional Reconfiguration Logic. Added list of PHY debugging features the parameter sets. Refer to HMC Controller IP Core Parameters.
  • Restricted list of allowed values for the CDR reference clock parameter to frequencies that support TX PLL xN bonding mode.
  • Added new data path response interface signal dp<n>_rsp_errstat[6:0]. This signal holds the value of the ERRSTAT field of the response packet from the external HMC. Refer to Application Response Interface.
  • Removed pll_powerdown output signal. Refer to Adding the External PLL and Signals on the Interface to the External PLL.
  • Updated description of dp<n>_rsp_error signal to indicate that the IP core now maintains the value of dp<n>_rsp_error for the duration of a multi-cycle transaction. Previously this behavior was not guaranteed. Refer to Application Response Interface.
  • Corrected description of dp<n>_rsp_cmd signal to clarify that it can hold only the non-error response codes from Table 25 in the HMC specification. Refer to Application Response Interface.
  • Added new Limit Outstanding FLITs feature for full-width variations to mitigate read response congestion. Added new LIMIT_OUTSTANDING_PACKET register to control the feature. Refer to Flow Control and LIMIT_OUTSTANDING_PACKETS Register.
  • Added software control for reset, link reinitialization, fatal error recovery, and power management. Added the following fields to the CONTROL register:
    • P_RST_N in bit [17]: software controlled reset of the HMC.
    • TXPS in bit [16]: Power management field.
    • SoftReset in bit [2]: software-controlled reset of the IP core.
    • Retrain in bit [0]: Restart IP core link initialization sequence.
    Refer to Initialization and Reset and CONTROL Register.
  • Corrected references to signal direction in description of hmc_lxtxps signal in HMC Interface Signals.
2015.05.04 15.0 Initial release.
Level Two Title