Hybrid Memory Cube Controller IP Core User Guide - Intel Stratix 10 Beta Version

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ID 683854
Date 8/08/2016
Public
Document Table of Contents
Document Table of Contents x
1. About the Hybrid Memory Cube Controller IP Core 2. Getting Started with the HMC Controller IP Core 3. Functional Description 4. HMC Controller IP Core Signals 5. HMC Controller IP Core Register Map 6. HMC Controller IP Core Stratix 10 Design Example A. HMC Controller IP Core User Guide Archives B. Additional Information
1. About the Hybrid Memory Cube Controller IP Core x
1.1. HMC Controller IP Core Supported Features 1.2. HMC Controller IP Core Supported HMC Transaction Types 1.3. Device Family Support 1.4. IP Core Verification 1.5. Performance and Resource Utilization 1.6. Device Speed Grade Support 1.7. Release Information
1.4. IP Core Verification x
1.4.1. Simulation
2. Getting Started with the HMC Controller IP Core x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying IP Core Parameters and Options 2.3. HMC Controller IP Core Parameters 2.4. Files Generated for Intel FPGA IP Cores 2.5. Integrating Your IP Core in Your Design 2.6. Simulating Intel FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.3. HMC Controller IP Core Parameters x
2.3.1. RX Mapping and TX Mapping Parameters
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Constraints 2.5.2. Required External Blocks
2.5.2. Required External Blocks x
2.5.2.1. Adding the External PLL 2.5.2.2. Adding the External I2C Master Module
3. Functional Description x
3.1. High Level Block Diagram 3.2. Interfaces Overview 3.3. Clocking Structure 3.4. Initialization and Reset 3.5. M20K ECC Support 3.6. Flow Control 3.7. Error Detection and Management 3.8. Testing Features
3.2. Interfaces Overview x
3.2.1. Application Interfaces 3.2.2. HMC Interface 3.2.3. Interface to External I2C Master 3.2.4. Control and Status Register Interface 3.2.5. Status and Debug Interface 3.2.6. Transceiver Control Interfaces
3.2.6. Transceiver Control Interfaces x
3.2.6.1. External PLL Interface 3.2.6.2. Transceiver Reconfiguration Interface
4. HMC Controller IP Core Signals x
4.1. Application Interface Signals 4.2. HMC Interface Signals 4.3. Signals on the Interface to the I2C Master 4.4. Control and Status Register Interface Signals 4.5. Status and Debug Signals 4.6. Clock and Reset Signals 4.7. Transceiver Reconfiguration Signals 4.8. Signals on the Interface to the External PLL
4.1. Application Interface Signals x
4.1.1. Application Request Interface 4.1.2. Application Response Interface 4.1.3. HMC Controller IP Core Data Path Example
5. HMC Controller IP Core Register Map x
5.1. CONTROL Register 5.2. XCVR_STATUS Register 5.3. LANE_STATUS Register 5.4. LINK_STATUS Register 5.5. ERROR_RESPONSE Register 5.6. LIMIT_OUTSTANDING_PACKETS Register 5.7. Interrupt Related Registers 5.8. Error and Retry Statistics Registers
B. Additional Information x
B.1. HMC Controller IP Core User Guide Revision History
1. About the Hybrid Memory Cube Controller IP Core
2. Getting Started with the HMC Controller IP Core
3. Functional Description
4. HMC Controller IP Core Signals
5. HMC Controller IP Core Register Map
6. HMC Controller IP Core Stratix 10 Design Example
A. HMC Controller IP Core User Guide Archives
B. Additional Information

2.5.2.2. Adding the External I2C Master Module

The HMC Controller IP core requires that you instantiate an external I2C master module in your design. Your design must include this module to initialize the HMC device to which your IP core connects. Alternatively, you can implement the required initialization sequence with a JTAG master module.

The I2C master module in your system must load the HMC device configuration registers according to the initialization requirements of the specific HMC device in your system.

The HMC specification requires that you set the HMC device REGISTER REQUEST commands register to the value of Init Continue after sending the commands to initialize the HMC. Therefore, the I2C master module must set this register to indicate successful completion of the HMC device configuration register load sequence.

In addition, the I2C master module must provide the following two signals to connect to the HMC Controller IP core:

  • An input signal that accepts requests to load the configuration registers of the HMC device. You must connect this signal to the HMC Controller IP core i2c_load_registers output signal. If multiple HMC Controller IP cores connect to the same HMC device, you must connect this input signal to the AND of the individual HMC Controller IP core i2c_load_registers output signals. You must provide the AND function.
  • An output signal that indicates successful completion of the configuration register load sequence. The I2C master must implement this signal with the following behavior:
    1. Deassert this signal when coming out of reset.
    2. Assert this signal after writing Init Continue to the HMC device REGISTER REQUEST commands register.
    3. Deassert this signal in response to the falling edge of the input signal described above.
    You must connect this signal to the HMC Controller IP core i2c_registers_loaded input signal. If multiple HMC Controller IP cores connect to the same HMC device, you must connect this signal to the i2c_registers_loaded signals of all of the HMC Controller IP cores.

For information about the required register configuration sequence, you must refer to the data sheet of the HMC device that is connected to your HMC Controller IP core. Recall that the HMC Controller IP core operates in Response Open Loop Mode, and you must configure the HMC device to communicate correctly with the IP core in this mode. In addition, because the IP core does not support the TGA field, you must configure the HMC device to respond to every non-posted Write request with a Write response packet.

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