AN 728: I/O PLL Reconfiguration and Dynamic Phase Shift for Intel® Arria® 10 and Intel Cyclone® 10 GX Devices

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ID 683845
Date 8/08/2022
Public
Document Table of Contents
Document Table of Contents x
I/O PLL Reconfiguration and Dynamic Phase Shift for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
I/O PLL Reconfiguration and Dynamic Phase Shift for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices x
Implementing I/O PLL Reconfiguration in the PLL Reconfig IP Core Implementing I/O PLL Dynamic Phase Shift in the IOPLL IP Core Design Considerations Using the Design Examples Document Revision History for AN 728: I/O PLL Reconfiguration and Dynamic Phase Shift for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
Implementing I/O PLL Reconfiguration in the PLL Reconfig IP Core x
Avalon® Memory-Mapped Interface Ports in the PLL Reconfig IP Core Connecting the IOPLL and PLL Reconfig IP Cores Connectivity between the IOPLL and PLL Reconfig IP Cores I/O PLL Reconfiguration Write Operation I/O PLL Reconfiguration Read Operation Address Bus and Data Bus Settings .mif Streaming Reconfiguration
I/O PLL Reconfiguration Write Operation x
Write Operation for .mif Streaming Reconfiguration
Address Bus and Data Bus Settings x
Address Bus and Data Bus Setting for Counter Setting Reconfiguration Address Bus and Data Bus Setting for Dynamic Phase Shift Address Bus and Data Bus Setting for Bandwidth Setting Reconfiguration Data Bus Setting for Loop Filter and Charge Pump Settings Address Bus and Data Bus Setting for .mif Streaming Reconfiguration
.mif Streaming Reconfiguration x
.mif File Format .mif Streaming Reconfiguration Operation Codes
Implementing I/O PLL Dynamic Phase Shift in the IOPLL IP Core x
Dynamic Phase Shift Ports in the IOPLL IP Core I/O PLL Dynamic Phase Shift Operation
Using the Design Examples x
Design Example 1: I/O PLL Reconfiguration Design Example 2: .mif Streaming Reconfiguration Design Example 3: I/O PLL Dynamic Phase Shift
I/O PLL Reconfiguration and Dynamic Phase Shift for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

Avalon® Memory-Mapped Interface Ports in the PLL Reconfig IP Core

Table 1.   Avalon® Memory-Mapped Interface Ports in the PLL Reconfig IP Core
Port Direction Description
mgmt_clk Input Dynamic reconfiguration clock that drives the PLL Reconfig IP core. This port must be connected to a valid clock source. The maximum input clock frequency is 100 MHz. This clock can be an independent clock source.
mgmt_reset Input Active high signal. This port is synchronous with mgmt_clk. Assert this reset input to clear all the data in the PLL Reconfig IP core.
mgmt_waitrequest Output This port goes high when PLL reconfiguration process started and remains high during PLL reconfiguration. After PLL reconfiguration process completed, this port goes low.
mgmt_read Input Active high signal. Asserts to indicate a read operation.
mgmt_write Input Active high signal. Asserts to indicate a write operation.
mgmt_readdata[31..0] Output Reads data from this port when mgmt_read signal is asserted.
mgmt_address[8..0] Input Specifies the address of the data bus for a read or write operation.
mgmt_writedata[31..0] Input Writes data to this port when mgmt_write signal is asserted.
mgmt_byteenable[3..0] Input Optional. Permits write operation to the PLL Reconfig IP core from an Avalon® memory-mapped interface with data bus width wider than 32 bits.
reconfig_from_pll[63..0] Input Bus that connects to reconfig_from_pll[63..0] bus in the IOPLL IP core.
reconfig_to_pll[63..0] Output Bus that connects to reconfig_to_pll[63..0] bus in the IOPLL IP core.
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