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Implementing I/O PLL Reconfiguration in the PLL Reconfig IP Core
Implementing I/O PLL Dynamic Phase Shift in the IOPLL IP Core
Design Considerations
Using the Design Examples
Document Revision History for AN 728: I/O PLL Reconfiguration and Dynamic Phase Shift for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
Avalon® Memory-Mapped Interface Ports in the PLL Reconfig IP Core
Connecting the IOPLL and PLL Reconfig IP Cores
Connectivity between the IOPLL and PLL Reconfig IP Cores
I/O PLL Reconfiguration Write Operation
I/O PLL Reconfiguration Read Operation
Address Bus and Data Bus Settings
.mif Streaming Reconfiguration
Address Bus and Data Bus Setting for Counter Setting Reconfiguration
Address Bus and Data Bus Setting for Dynamic Phase Shift
Address Bus and Data Bus Setting for Bandwidth Setting Reconfiguration
Data Bus Setting for Loop Filter and Charge Pump Settings
Address Bus and Data Bus Setting for .mif Streaming Reconfiguration
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.mif Streaming Reconfiguration
The .mif file stores the commands as ROM in M20K embedded memory block. You can send these commands to the PLL Reconfig IP core via .mif streaming reconfiguration.
Each .mif streaming reconfiguration must be indicated with the Start of .mif (SOM) and End of .mif (EOM) operation codes.
The .mif streaming reconfiguration starts at the .mif base address that you specify. The PLL Reconfig IP core reads the .mif file contents until it encounters a SOM operation code (Opcode). From this point, the .mif streaming reconfiguration simulates the commands that the user logic could send to the PLL Reconfig IP core. These commands are address-data pairs in the .mif file specifying the setting to be reconfigured to the new value. The address is stored as an Opcode in the lower nine bits of each entry word, while data is stored in the lower 18 bits of each entry word. The bit settings for address-data pairs in the .mif file is the same as the address bus and data bus bit setting for counter setting reconfiguration and bandwidth setting reconfiguration. The .mif streaming reconfiguration ends when the EOM Opcode is encountered.
You can save multiple I/O PLL configurations in a .mif file if you mark the SOM and EOM Opcodes appropriately. The PLL Reconfig IP core reads the setting from ROM in M20K embedded memory block, which has default address width = 9 bits and data width = 32 bits with total of 512 words. These sizes can change as parameters are passed to the top-level module. For .mif streaming reconfiguration, data width must be 32 bits to match the PLL Reconfig IP core.
Intel recommends using a .mif file generated from the IOPLL IP core with the desired reconfiguration setting. The generated .mif file stores the entire I/O PLL profile.