AN 728: I/O PLL Reconfiguration and Dynamic Phase Shift for Intel® Arria® 10 and Intel Cyclone® 10 GX Devices

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ID 683845
Date 8/08/2022
Public
Document Table of Contents
Document Table of Contents x
I/O PLL Reconfiguration and Dynamic Phase Shift for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
I/O PLL Reconfiguration and Dynamic Phase Shift for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices x
Implementing I/O PLL Reconfiguration in the PLL Reconfig IP Core Implementing I/O PLL Dynamic Phase Shift in the IOPLL IP Core Design Considerations Using the Design Examples Document Revision History for AN 728: I/O PLL Reconfiguration and Dynamic Phase Shift for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
Implementing I/O PLL Reconfiguration in the PLL Reconfig IP Core x
Avalon® Memory-Mapped Interface Ports in the PLL Reconfig IP Core Connecting the IOPLL and PLL Reconfig IP Cores Connectivity between the IOPLL and PLL Reconfig IP Cores I/O PLL Reconfiguration Write Operation I/O PLL Reconfiguration Read Operation Address Bus and Data Bus Settings .mif Streaming Reconfiguration
I/O PLL Reconfiguration Write Operation x
Write Operation for .mif Streaming Reconfiguration
Address Bus and Data Bus Settings x
Address Bus and Data Bus Setting for Counter Setting Reconfiguration Address Bus and Data Bus Setting for Dynamic Phase Shift Address Bus and Data Bus Setting for Bandwidth Setting Reconfiguration Data Bus Setting for Loop Filter and Charge Pump Settings Address Bus and Data Bus Setting for .mif Streaming Reconfiguration
.mif Streaming Reconfiguration x
.mif File Format .mif Streaming Reconfiguration Operation Codes
Implementing I/O PLL Dynamic Phase Shift in the IOPLL IP Core x
Dynamic Phase Shift Ports in the IOPLL IP Core I/O PLL Dynamic Phase Shift Operation
Using the Design Examples x
Design Example 1: I/O PLL Reconfiguration Design Example 2: .mif Streaming Reconfiguration Design Example 3: I/O PLL Dynamic Phase Shift
I/O PLL Reconfiguration and Dynamic Phase Shift for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

Address Bus and Data Bus Setting for Counter Setting Reconfiguration

Table 2.  Address Bus and Data Bus Bit Setting for Counter Setting Reconfiguration using the PLL Reconfig IP Core
Counter Name Address Bus Bit Setting (Binary) Data bus bit setting (Binary)
M 9’b010010000
  • Data[7..0] = low_div
  • Data[15..8] = high_div
  • total_div = high_div + low_div
  • Data[16] = bypass enable
    • When Data[16] = 1, bypass is enabled. The selected counter is bypassed with counter division value=1.
  • Data[17] = odd division
    • When Data[17] = 0, odd division is disabled. The selected counter duty cycle = high_div/total_div.
    • When Data[17] = 1, odd division is enabled. The selected counter duty cycle = (high_div - 0.5)/total_div.
N 9’b010100000
C0 9’b011000000
C1 9’b011000001
C2 9’b011000010
C3 9’b011000011
C4 9’b011000100
C5 9’b011000101
C6 9’b011000110
C7 9’b011000111
C8 9’b011001000
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