AN 728: I/O PLL Reconfiguration and Dynamic Phase Shift for Intel® Arria® 10 and Intel Cyclone® 10 GX Devices

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ID 683845
Date 8/08/2022
Public
Document Table of Contents
Document Table of Contents x
I/O PLL Reconfiguration and Dynamic Phase Shift for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
I/O PLL Reconfiguration and Dynamic Phase Shift for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices x
Implementing I/O PLL Reconfiguration in the PLL Reconfig IP Core Implementing I/O PLL Dynamic Phase Shift in the IOPLL IP Core Design Considerations Using the Design Examples Document Revision History for AN 728: I/O PLL Reconfiguration and Dynamic Phase Shift for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
Implementing I/O PLL Reconfiguration in the PLL Reconfig IP Core x
Avalon® Memory-Mapped Interface Ports in the PLL Reconfig IP Core Connecting the IOPLL and PLL Reconfig IP Cores Connectivity between the IOPLL and PLL Reconfig IP Cores I/O PLL Reconfiguration Write Operation I/O PLL Reconfiguration Read Operation Address Bus and Data Bus Settings .mif Streaming Reconfiguration
I/O PLL Reconfiguration Write Operation x
Write Operation for .mif Streaming Reconfiguration
Address Bus and Data Bus Settings x
Address Bus and Data Bus Setting for Counter Setting Reconfiguration Address Bus and Data Bus Setting for Dynamic Phase Shift Address Bus and Data Bus Setting for Bandwidth Setting Reconfiguration Data Bus Setting for Loop Filter and Charge Pump Settings Address Bus and Data Bus Setting for .mif Streaming Reconfiguration
.mif Streaming Reconfiguration x
.mif File Format .mif Streaming Reconfiguration Operation Codes
Implementing I/O PLL Dynamic Phase Shift in the IOPLL IP Core x
Dynamic Phase Shift Ports in the IOPLL IP Core I/O PLL Dynamic Phase Shift Operation
Using the Design Examples x
Design Example 1: I/O PLL Reconfiguration Design Example 2: .mif Streaming Reconfiguration Design Example 3: I/O PLL Dynamic Phase Shift
I/O PLL Reconfiguration and Dynamic Phase Shift for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

Document Revision History for AN 728: I/O PLL Reconfiguration and Dynamic Phase Shift for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

Document Version Changes
2022.08.08
  • Updated the Implementing I/O PLL Dynamic Phase Shift in the IOPLL IP Core section.
  • Renamed Avalon-MM interface to Avalon memory-mapped interface.
2019.04.03 Updated the charge pump setting for M counter total division value 4–5 (high bandwidth) and 16–23 (medium bandwidth) in the Data Bus Setting for Loop Filter and Charge Pump Settings table.
2018.06.15
  • Added support for Intel® Cyclone® 10 GX devices.
  • Updated the description for the mgmt_reset port in the Avalon® -MM Interface Ports in the PLL Reconfig IP Core table.
  • Renamed the following IP cores as per Intel rebranding:
    • Renamed Altera PLL Reconfig IP core to PLL Reconfig Intel FPGA IP core.
    • Renamed Altera IOPLL IP core to IOPLL Intel FPGA IP core.
    • Renamed Altera In-System Sources & Probe IP core to In-System Sources & Probes Intel FPGA IP core.
  • Updated the following terms:
    • Updated Quartus Prime to Intel Quartus Prime.
    • Updated TimeQuest Timing Analyzer to Timing Analyzer.
    • Updated Qsys to Platform Designer.
Date Version Changes
March 2017 2017.03.15 Rebranded as Intel.
May 2016 2016.05.05
  • Updated the definition for mgmt_reset in Avalon-MM Interface Ports in Altera PLL Reconfig IP Core table.
  • Changed instances of Quartus II to Quartus Prime.
June 2015 2015.06.12
  • Added description to the introduction section that you must ensure the reconfigured PLL settings are within the legal range.
  • Added description to the I/O PLL Reconfiguration Read Operation topic: An I/O PLL reconfiguration read operation requires at least three mgmt_clk cycles of latency.
  • Restructured and updated Design Considerations section.
  • Added Design Examples section.
January 2015 2015.01.23 Initial release.
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