AN 728: I/O PLL Reconfiguration and Dynamic Phase Shift for Intel® Arria® 10 and Intel Cyclone® 10 GX Devices

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ID 683845
Date 8/08/2022
Public
Document Table of Contents
Document Table of Contents x
I/O PLL Reconfiguration and Dynamic Phase Shift for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
I/O PLL Reconfiguration and Dynamic Phase Shift for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices x
Implementing I/O PLL Reconfiguration in the PLL Reconfig IP Core Implementing I/O PLL Dynamic Phase Shift in the IOPLL IP Core Design Considerations Using the Design Examples Document Revision History for AN 728: I/O PLL Reconfiguration and Dynamic Phase Shift for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
Implementing I/O PLL Reconfiguration in the PLL Reconfig IP Core x
Avalon® Memory-Mapped Interface Ports in the PLL Reconfig IP Core Connecting the IOPLL and PLL Reconfig IP Cores Connectivity between the IOPLL and PLL Reconfig IP Cores I/O PLL Reconfiguration Write Operation I/O PLL Reconfiguration Read Operation Address Bus and Data Bus Settings .mif Streaming Reconfiguration
I/O PLL Reconfiguration Write Operation x
Write Operation for .mif Streaming Reconfiguration
Address Bus and Data Bus Settings x
Address Bus and Data Bus Setting for Counter Setting Reconfiguration Address Bus and Data Bus Setting for Dynamic Phase Shift Address Bus and Data Bus Setting for Bandwidth Setting Reconfiguration Data Bus Setting for Loop Filter and Charge Pump Settings Address Bus and Data Bus Setting for .mif Streaming Reconfiguration
.mif Streaming Reconfiguration x
.mif File Format .mif Streaming Reconfiguration Operation Codes
Implementing I/O PLL Dynamic Phase Shift in the IOPLL IP Core x
Dynamic Phase Shift Ports in the IOPLL IP Core I/O PLL Dynamic Phase Shift Operation
Using the Design Examples x
Design Example 1: I/O PLL Reconfiguration Design Example 2: .mif Streaming Reconfiguration Design Example 3: I/O PLL Dynamic Phase Shift
I/O PLL Reconfiguration and Dynamic Phase Shift for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

Dynamic Phase Shift Ports in the IOPLL IP Core

Figure 3. Dynamic Phase Shift Port Ports in the IOPLL IP Core
Table 8.  Dynamic Phase Shift Ports in the IOPLL IP Core
Port Direction Description
scanclk Input Dynamic phase shift clock that drives the IOPLL IP core dynamic phase shift operation. This port must be connected to a valid clock source. The maximum input clock frequency is 100 MHz.
phase_en Input Active high signal. Asserts to start the dynamic phase shift operation.
updn Input Determines the direction of dynamic phase shift. When updn = 0, phase shift is in negative direction (shift down). When updn = 1, phase shift is in positive direction (shift up).
cntsel[4..0] Input
Determines the counter to be selected to perform dynamic phase shift operation.
Counter Name cntsel[4..0] (Binary)
C0 5’b00000
C1 5’b00001
C2 5’b00010
C3 5’b00011
C4 5’b00100
C5 5’b00101
C6 5’b00110
C7 5’b00111
C8 5’b01000
All C counters 5’b01111
num_phase_shift[2..0] Input Determines the number of phase shifts per dynamic phase shift operation. Up to seven phase shifts per operation are possible. Each phase shift step is equal to 1/8 of I/O PLL VCO period.
phase_done Output The IOPLL IP core drives this port high for one scanclk cycle after dynamic phase shift operation is complete.
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