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Implementing I/O PLL Reconfiguration in the PLL Reconfig IP Core
Implementing I/O PLL Dynamic Phase Shift in the IOPLL IP Core
Design Considerations
Using the Design Examples
Document Revision History for AN 728: I/O PLL Reconfiguration and Dynamic Phase Shift for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
Avalon® Memory-Mapped Interface Ports in the PLL Reconfig IP Core
Connecting the IOPLL and PLL Reconfig IP Cores
Connectivity between the IOPLL and PLL Reconfig IP Cores
I/O PLL Reconfiguration Write Operation
I/O PLL Reconfiguration Read Operation
Address Bus and Data Bus Settings
.mif Streaming Reconfiguration
Address Bus and Data Bus Setting for Counter Setting Reconfiguration
Address Bus and Data Bus Setting for Dynamic Phase Shift
Address Bus and Data Bus Setting for Bandwidth Setting Reconfiguration
Data Bus Setting for Loop Filter and Charge Pump Settings
Address Bus and Data Bus Setting for .mif Streaming Reconfiguration
Visible to Intel only — GUID: mcn1418357573964
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.mif Streaming Reconfiguration Operation Codes
| Operation Name | Operation Code | Description |
|---|---|---|
| Start of .mif (SOM) | 9’b000011110 | Indicates start of I/O PLL reconfiguration. |
| End of .mif (EOM) | 9’b000011111 | Indicates end of I/O PLL reconfiguration. |